884 lines
30 KiB
C++
884 lines
30 KiB
C++
#pragma once
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#include <spider/SpiderRuntime.hpp>
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#include <spider/runtime/cpu/Register.hpp>
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namespace spider {
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class CPU {
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public: // Helper types
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using Fn = void (CPU::*)();
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public: // Flag Register Constants //
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static constexpr const u64 FLAG_ENABLE = 0b0000000000000000000000000000000000000000000000000000000000000001;
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static constexpr const u64 FLAG_INTERRUPT_SIGNAL = 0b0000000000000000000000000000000000000000000000000000000000000010;
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static constexpr const u64 FLAG_INTERRUPT_REQUEST = 0b0000000000000000000000000000000000000000000000000000000000000100;
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static constexpr const u64 FLAG_EXCEPTION = 0b0000000000000000000000000000000000000000000000000000000000001000;
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static constexpr const u64 FLAG_MEMORY_MODE = 0b0000000000000000000000000000000000000000000000000000000000110000;
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public: // Map of addressing modes & Instructions
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static CPU::Fn addrModes[];
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static CPU::Fn instrMap[];
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public: // General Purpose Registers
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union {
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register_t GPR[16];
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struct {
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register_t RA, RB, RC, RD,
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RX, RY, R0, R1,
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R2, R3, R4, R5,
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R6, R7, R8, R9;
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};
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};
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public: // System Registers
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u64 RF;
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u64 RI;
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u64 RS;
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u64 RZ;
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u64 RE;
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u64 RN; // Epsilo(n)
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u64 RV;
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u64 RM;
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public:
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/**
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* These are private registers, which are only used
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* whenever constant things are used.
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* This way we don't "write" into constant values, rather
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* we write into a writeable var which is "hidden"
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*/
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register_t ALU0, ALU1;
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union {
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struct {
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register_t* _dst;
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register_t* _src;
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register_t* _alu;
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};
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register_t* _opers[2];
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};
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// Holds the current instruction opcode
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u16 _opcode : 9;
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// Holds the current addressing modes,
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// before they were used
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u8 _addrm : 5;
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// Holds the current instruction size.
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u8 _size : 2;
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// On _post that are not no-ops, it must
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// write back DST to this memory location.
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u64 _store;
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// Post execution callback
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CPU::Fn _post;
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private:
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/**
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* Pointer to the current RAM hooked into
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* the CPU.
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*
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* It is unproved whether having the RAM directly
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* into the CPU is better than not, or whether a
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* virtual BUS is better.
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*
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* Alas, this way we can have a CPU state switch
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* between memory and instruction banks.
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*/
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RAM* _ram;
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/**
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* Pointer to the current Instruction Reel
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* hooked into the CPU.
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*
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* Ditto as RAM.
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*/
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InstrReel* _reel;
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public:
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CPU();
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CPU(const CPU& other) = default;
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CPU(CPU&& other) noexcept = default;
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~CPU();
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public:
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CPU& operator=(const CPU& other) = default;
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CPU& operator=(CPU&& other) noexcept = default;
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public:
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void hookRAM(RAM* ram);
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void hookInstrReel(InstrReel* reel);
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constexpr u64 getFlag(u64 mask);
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public:
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/**
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* Fetches the instruction from the
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* reel, and advances IR by two.
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*/
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void fetchInstr();
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/**
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* Fetches the destination operand,
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* by calling the appropriate addressing
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* mode.
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*
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* Will read the bottom 3 bits.
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* For instructions with two operands,
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* call Src first.
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*
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* The internal variable _addrm
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* will not be modified. It will
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* be important when writing
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* back the result.
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*/
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void fetchOperDst();
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/**
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* Fetches the source operand.
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*
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* For use in two operand instructions.
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*
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* Will read the bottom 3 bits. It will
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* then shift the _addrm 3 spaces
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* to ensure it aligns with the DST
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* next.
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*
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* Additionally, it will add 1 to _addrm
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* to account with
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*/
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void fetchOperSrc();
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/**
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* Executes an opcode, by means of directly
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* accessing the instruction map and
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* calling that function pointer.
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*/
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void execute();
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/**
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* Executes an opcode, by means of using
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* a large switch statement. Only suitable
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* for environments where the instruction
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* map is not possible.
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*
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* This has yet to be proved!!!
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*/
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void executeSwLk();
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public: // Addressing Modes
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/**
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* Implied Addressing Mode
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*/
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void imp(); // Kept as it is a no-op
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/**
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* Immediate Addressing Mode
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*/
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void imm();
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/**
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* Absolute Addressing Mode
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*/
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void abs();
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/**
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* Register Addressing Mode
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*/
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void reg();
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/**
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* Indrect Addressing Mode
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*/
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void ind();
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/**
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* Pointer Addressing Mode
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*/
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void ptr();
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/**
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* Indexed Addressing Mode
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*/
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void idx();
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/**
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* Scaled Addressing Mode
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*/
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void sca();
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/**
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* Displaced Addressing Mode
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*/
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void dis();
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/**
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* Post-Write Action
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*/
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void psw();
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public:
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// <pygen-target name=cpu-instructions> //
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// [System] 0x000 — NOP: No Operation
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation: Nothing
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void NOP();
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// [System] 0x001 — SPDR: Will place the Spider version of the interpreter in RA
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation: (Spider Version) -> RA
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void SPDR();
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// [System] 0x002 — MMODE: Set Memory Mode
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// Params: 1 | AddrMask1: 05 AddrMask2: 00 | TypeMask: 01
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// Operation: Dst -> Memory Mode Bits
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void MMODE();
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// [System] 0x003 — INT: Interrupt
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// Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 08
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// Operation: Performs system interrupt no. (Dst) (See table)
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void INT();
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// [System] 0x004 — LRV: Load Interrupt Vector Register
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// Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 08
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// Operation: Dst -> RV
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void LRV();
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// [System] 0x005 — FSR: Fetch System Register
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 08
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// Operation: System Register at Dst -> Dst
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void FSR();
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// [System] 0x006 — FIR: Fetch Instruction Register
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 08
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// Operation: Instruction Register -> Dst
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void FIR();
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// [System] 0x007 — FZR: Fetch Stack Base Register
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 08
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// Operation: Stack Base Register -> Dst
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void FZR();
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// [System] 0x008 — LSR: Load System Register
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// Params: 2 | AddrMask1: 1E AddrMask2: 1F | TypeMask: 08
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// Operation: Src -> System Register at Dst
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void LSR();
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// [System] 0x009 — FVR: Fetch Interrupt Vector Register
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// Params: 1 | AddrMask1: 04 AddrMask2: 00 | TypeMask: 08
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// Operation: Interrupt Vector Register -> Dst
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void FVR();
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// [Memory] 0x00A — MOV: Moves values
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src -> Dst
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void MOV();
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// [Memory] 0x00B — MOR: Moves registers
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// Params: 2 | AddrMask1: 04 AddrMask2: 04 | TypeMask: 08
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// Operation: R Scr -> R Dst
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void MOR();
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// [Memory] 0x00C — AMOV: Array Move, uses X and Y as ptrs, A as amount
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 08
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// Operation: Array from X to Y, by A amount
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void AMOV();
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// [Memory] 0x00D — SWP: Swap registers
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// Params: 2 | AddrMask1: 04 AddrMask2: 04 | TypeMask: 08
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// Operation: Src <-> Dst
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void SWP();
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// [Memory] 0x00E — AHM: Ask Host for Memory
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// Params: 1 | AddrMask1: 04 AddrMask2: 00 | TypeMask: 08
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// Operation: Asks the host for a specific size of memory. Responds with 0 or 1
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void AHM();
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// [Integer] 0x010 — COM: One's complement
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: ~ Dst -> Dst
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void COM();
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// [Integer] 0x011 — NEG: Two's complement
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: - Dst -> Dst
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void NEG();
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// [Integer] 0x012 — EXS: Extend Sign
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Last bit is copied and expanded for the next int size
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void EXS();
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// [Integer] 0x013 — INC: Increment
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + 1 -> Dst
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void INC();
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// [Integer] 0x014 — DEC: Decrement
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst - 1 -> Dst
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void DEC();
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// [Integer] 0x015 — ADD: Addition
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst + Src -> Dst
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void ADD();
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// [Integer] 0x016 — SUB: Subtraction
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst - Src-> Dst
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void SUB();
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// [Integer] 0x017 — MUL: Multiplication
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst * Src -> Dst
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void MUL();
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// [Integer] 0x018 — UMUL: Unsigned Multiplication
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst * Src -> Dst
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void UMUL();
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// [Integer] 0x019 — DIV: Division
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst / Src -> Dst
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void DIV();
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// [Integer] 0x01A — UDIV: Unsigned Division
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst / Src -> Dst
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void UDIV();
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// [Integer] 0x01B — MOD: Modulus
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst % Src -> Dst
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void MOD();
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// [Integer] 0x01C — UMOD: Unsigned Modulus
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst % Src -> Dst
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void UMOD();
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// [Integer] 0x01D — DMOD: Division and Modulus
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst / Src -> X, Dst % Src -> Y
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void DMOD();
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// [Integer] 0x01E — UDMD: Unsigned Division and Modulus
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst / Src -> X, Dst % Src -> Y
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void UDMD();
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// [System] 0x01F — FBT: Test and update Flag Register (Integer) Bits
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Flags of Dst -
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void FBT();
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// [Bit Wise] 0x020 — STB: Set Bit
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src# bit is set on Dst
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void STB();
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// [Bit Wise] 0x021 — CRB: Clear Bit
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src# bit is cleared on Dst
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void CRB();
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// [Bit Wise] 0x022 — TSB: Test Bit
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src# bit is tested against Dst, updates Equal Flag
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void TSB();
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// [Bit Wise] 0x023 — BOOL: Sets the booleaness of a value
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Tests Dst != 0, updates Equal Flag
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void BOOL();
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// [Bit Wise] 0x024 — NOT: Sets the inverse booleaness of a value (! BOOL)
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Tests Dst == 0, updates Equal Flag
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void NOT();
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// [Bit Wise] 0x025 — AND: Boolean AND operation
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst AND Src into Dst
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void AND();
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// [Bit Wise] 0x026 — OR: Boolean OR operation
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst OR Src into Dst
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void OR();
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// [Bit Wise] 0x027 — XOR: Boolean XOR operation
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst XOR Src into Dst
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void XOR();
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// [Bit Wise] 0x028 — SHL: Arithmetic Shift Left
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst << Src into Dst
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void SHL();
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// [Bit Wise] 0x029 — SHR: Arithmetic Shift Right
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst >> Src into Dst
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void SHR();
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// [Bit Wise] 0x02A — SSR: Signed Shift Right
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst >>> Src into Dst
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void SSR();
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// [Bit Wise] 0x02B — ROL: Rotate Left
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst ROL Src into Dst
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void ROL();
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// [Bit Wise] 0x02C — ROR: Rotate Right
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst ROR Src into Dst
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void ROR();
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// [Bit Wise] 0x02D — CNT: Counts bits
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: # of 1's into Dst
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void CNT();
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// [Boolean] 0x030 — EQ: Equal
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst == Src into Dst
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void EQ();
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// [Boolean] 0x031 — NE: Not Equal
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst != Src into Dst
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void NE();
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// [Boolean] 0x032 — GT: Greater Than
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst > Src into Dst
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void GT();
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// [Boolean] 0x033 — GE: Greater or Equal Than
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst >= Src into Dst
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void GE();
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// [Boolean] 0x034 — LT: Lower Than
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst < Src into Dst
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void LT();
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// [Boolean] 0x035 — LE: Lower or Equal Than
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst <= Src into Dst
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void LE();
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// [Branch] 0x038 — JMP: Jump to absolute position
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> Instruction Register
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void JMP();
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// [Branch] 0x039 — JEQ: Jumps to position if EQ flag is set
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> Instruction Register IF Flags.EQ
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void JEQ();
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// [Branch] 0x03A — JNE: Jumps to position if EQ flag is cleared
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> Instruction Register IF NOT Flags.EQ
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void JNE();
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// [Branch] 0x03B — JIF: Jumps if value provided is booleanly true
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst -> Instruction Register IF Src
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void JIF();
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// [Branch] 0x03C — JMR: Jump Relative
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register
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void JMR();
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// [Branch] 0x03D — JER: Jumps to relative position if EQ flag is set
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register IF Flags.EQ
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void JER();
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// [Branch] 0x03E — JNR: Jumps to relative position if EQ flag is cleared
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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|
// Operation: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ
|
|
void JNR();
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// [Branch] 0x03F — JIR: Jumps to relative position if value provided is booleanly true
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register IF Src
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void JIR();
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// [System] 0x040 — SFB: Store (User) Flag Bit
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void SFB();
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// [System] 0x041 — LFB: Load (User) Flag Bit
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|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void LFB();
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// [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void JUF();
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// [Branch] 0x043 — JUR: Jump to relative position, if user flag is true
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void JUR();
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// [Memory] 0x044 — PUSH: Push to stack
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> pushed into stack
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void PUSH();
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// [Memory] 0x045 — POP: Pop from stack
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|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: popped from stack -> Dst
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void POP();
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// [Memory] 0x046 — ALLOC: Allocate to heap
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> heap ptr of size Dst
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void ALLOC();
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// [Memory] 0x047 — HFREE: Delete from heap
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|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Frees heap ptr in Dst
|
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void HFREE();
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// [Branch] 0x04A — CALL: Call function at instruction index
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|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Performs a function call, step XX
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void CALL();
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// [Branch] 0x04B — RET: Return from a function
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|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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|
// Operation: Undoes a function call, step XX
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|
void RET();
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// [System] 0x04C — EDI: Enable/Disable External Interrupts
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|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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|
// Operation: bool( Dst ) -> Enable External Interrupts Bit
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|
void EDI();
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// [System] 0x04D — SHSS: Set Hotswap Signal Bit
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|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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|
// Operation: bool( Dst ) -> Hot Swap Signal Bit
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|
void SHSS();
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// [Floating Point] 0x050 — FLI: Float Load Immediate
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
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// Operation:
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void FLI();
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// [Floating Point] 0x051 — FNEG: Float negate
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
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// Operation: - Dst -> Dst
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|
void FNEG();
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// [Floating Point] 0x052 — FADD: Float add
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|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst + Src -> Dst
|
|
void FADD();
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// [Floating Point] 0x053 — FSUB: Float subtract
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst - Src-> Dst
|
|
void FSUB();
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|
// [Floating Point] 0x054 — FMUL: Float multiplication
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst * Src -> Dst
|
|
void FMUL();
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|
// [Floating Point] 0x055 — FDIV: Float division
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
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|
// Operation: Dst / Src -> Dst
|
|
void FDIV();
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// [Floating Point] 0x056 — FMOD: Float modulus
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst % Src -> Dst
|
|
void FMOD();
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|
// [Floating Point] 0x057 — FDMOD: Float division and modulus
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst / Src -> X, Dst % Src -> Y
|
|
void FDMOD();
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|
|
|
// [Floating Point] 0x058 — FEPS: Sets the float epsilon value, for comparison
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: Dst -> Epsilon Register
|
|
void FEPS();
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|
|
|
// [Floating Point] 0x059 — FEEP: Float Enable/Disable Epsilon
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: bool( Dst ) -> Epsilon Enable Bit
|
|
void FEEP();
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|
|
|
// [Boolean] 0x05A — FEQ: Float Equal
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst == Src into Dst
|
|
void FEQ();
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|
|
|
// [Boolean] 0x05B — FNE: Float Not Equal
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst != Src into Dst
|
|
void FNE();
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|
|
|
// [Boolean] 0x05C — FGT: Float Greater Than
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst > Src into Dst
|
|
void FGT();
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|
|
|
// [Boolean] 0x05D — FGE: Float Greater or Equal Than
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst >= Src into Dst
|
|
void FGE();
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|
|
|
// [Boolean] 0x05E — FLT: Float Lower Than
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst < Src into Dst
|
|
void FLT();
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|
|
|
// [Boolean] 0x05F — FLE: Float Lower or Equal Than
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: Dst <= Src into Dst
|
|
void FLE();
|
|
|
|
// [Casts] 0x060 — F2D: F32 (Float) to F64 (Double)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void F2D();
|
|
|
|
// [Casts] 0x061 — D2F: F64 (Double) to F32 (Float)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void D2F();
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|
|
|
// [Casts] 0x062 — I2F: I32 (Integer) to F32 (Float)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void I2F();
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|
|
|
// [Casts] 0x063 — I2D: I32 (Integer) to F64 (Double)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void I2D();
|
|
|
|
// [Casts] 0x064 — L2F: I64 (Long) to F32 (Float)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void L2F();
|
|
|
|
// [Casts] 0x065 — L2D: I64 (Long) to F64 (Double)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void L2D();
|
|
|
|
// [Casts] 0x066 — F2I: F32 (Float) to I32 (Integer)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void F2I();
|
|
|
|
// [Casts] 0x067 — F2L: F32 (Float) to I64 (Long)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void F2L();
|
|
|
|
// [Casts] 0x068 — D2I: F64 (Double) to I32 (Integer)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void D2I();
|
|
|
|
// [Casts] 0x069 — D2L: F64 (Double) to I64 (Long)
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
|
// Operation: (cast) Dst -> Dst
|
|
void D2L();
|
|
|
|
// [Trigonometric] 0x06C — SIN: Sine Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: sin( Dst ) -> Dst
|
|
void SIN();
|
|
|
|
// [Trigonometric] 0x06D — COS: Cosine Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: cos( Dst ) -> Dst
|
|
void COS();
|
|
|
|
// [Trigonometric] 0x06E — TAN: Tangent Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: tan( Dst ) -> Dst
|
|
void TAN();
|
|
|
|
// [Trigonometric] 0x06F — ASIN: Arc Sine Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: asin( Dst ) -> Dst
|
|
void ASIN();
|
|
|
|
// [Trigonometric] 0x070 — ACOS: Arc Cosine Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: acos( Dst ) -> Dst
|
|
void ACOS();
|
|
|
|
// [Trigonometric] 0x071 — ATAN: Arc Tangent Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: atan( Dst ) -> Dst
|
|
void ATAN();
|
|
|
|
// [Trigonometric] 0x072 — ATAN2: Arc Tangent Function with 2 Arguments
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: atan( Dst, Src ) -> Dst
|
|
void ATAN2();
|
|
|
|
// [Exponential] 0x074 — EXP: Exponential Function
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: exp( Dst ) -> Dst
|
|
void EXP();
|
|
|
|
// [Exponential] 0x075 — LOG: Natural Logarithm
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: ln( Dst ) -> Dst
|
|
void LOG();
|
|
|
|
// [Exponential] 0x076 — LOGAB: Logarithm A of B
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: log( Dst, Src ) -> Dst
|
|
void LOGAB();
|
|
|
|
// [Exponential] 0x077 — POW: Power Function
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: pow( Dst, Src ) -> Dst
|
|
void POW();
|
|
|
|
// [Exponential] 0x078 — SQRT: Square Root
|
|
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
|
// Operation: sqrt( Dst ) -> Dst
|
|
void SQRT();
|
|
|
|
// [Exponential] 0x079 — ROOT: General Root
|
|
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
|
// Operation: pow( Dst, 1 / Src ) -> Dst
|
|
void ROOT();
|
|
|
|
// [Integer] 0x07C — ADC: Add with Carry
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation: Dst + Src + Flags.Carry -> Dst, Flags.Carry
|
|
void ADC();
|
|
|
|
// [Integer] 0x07D — SWC: Subtract with Carry (Borrow)
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation: Dst - Src - Flags.Carry -> Dst, Flags.Carry
|
|
void SWC();
|
|
|
|
// [Integer] 0x07E — MWO: Multiply with Overflow
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation: Signed Dst * Src -> Dst, Flags.Carry
|
|
void MWO();
|
|
|
|
// [Integer] 0x07F — UMO: Unsigned Multiply with Overflow
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation: Unsigned Dst * Src -> Dst, Flags.Carry
|
|
void UMO();
|
|
|
|
// [Matrix] 0x080 — MADD: Matrix Addition
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void MADD();
|
|
|
|
// [Matrix] 0x081 — MSUB: Matrix Subtraction
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void MSUB();
|
|
|
|
// [Matrix] 0x082 — MMUL: Matrix Multiply
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void MMUL();
|
|
|
|
// [Matrix] 0x083 — MINV: Matrix Inverse
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void MINV();
|
|
|
|
// [Matrix] 0x084 — MTRA: Matrix Transpose
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void MTRA();
|
|
|
|
// [Matrix] 0x085 — MDET: Matrix Determinant
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void MDET();
|
|
|
|
// [Quaternion] 0x086 — QMKA: Quaternion Make from Angles
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void QMKA();
|
|
|
|
// [Quaternion] 0x087 — QMUL: Quaternion Multiply
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void QMUL();
|
|
|
|
// [SIMD] 0x08A — XADD: SIMD Addition
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void XADD();
|
|
|
|
// [SIMD] 0x08B — XSUB: SIMD Subtract
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void XSUB();
|
|
|
|
// [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void XAMA();
|
|
|
|
// [SIMD] 0x08D — XMUL: SIMD Multiply
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void XMUL();
|
|
|
|
// [SIMD] 0x08E — XDIV: SIMD Divide
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void XDIV();
|
|
|
|
// [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory
|
|
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
|
// Operation:
|
|
void UPY();
|
|
|
|
// </pygen-target> //
|
|
|
|
};
|
|
|
|
}
|