Merge pull request 'Implement instructions 0x03C-0x053, add flag constants and fix execute pipeline' (#5) from diego/instruc-03c-053 into main

Reviewed-on: #5

src/spider/runtime/Runtime.cpp

@@ -17,8 +17,10 @@ namespace spider {
     // Stepping/Running the Machine //
 
     void Runtime::step() {
+        // fetchInstr() decodes the opcode, addressing mode and type siz
         cpu.fetchInstr();
-        // TODO: Call instruction
+        // execute() completes the fetch-decode-execute cycle by calling the correct instruction method based on the opcode.
+        cpu.execute();
     }
 
     void Runtime::step(u64 n) {

src/spider/runtime/cpu/CPU.cpp

@@ -1,187 +1,33 @@
 #include "CPU.hpp"
 
-#include <spider/runtime/native/machine.hpp>
-
-#include <spider/runtime/memory/RAM.hpp>
-#include <spider/runtime/memory/Types.hpp>
-
-#include <spider/runtime/reel/InstrReel.hpp>
-
-#if __cplusplus >= 202002L
-#include <bit>
-#endif
-
 namespace spider {
 
     CPU::CPU()
-        : RA{}, RB{}, RC{}, RD{},
-          RX{}, RY{}, R0{}, R1{},
-          R2{}, R3{}, R4{}, R5{},
-          R6{}, R7{}, R8{}, R9{},
-          RF{}, RI{}, RS{}, RZ{},
-          RE{}, RN{}, RV{}, RM{},
-          ALU0{}, ALU1{},
-        _dst(nullptr), _src(nullptr),
-        _opcode(0), _addrm(0), _size(0),
-        _store(0), _post(&CPU::imp),
-        _ram(nullptr), _reel(nullptr) {
-    }
+    :   RA{}, RB{}, RC{}, RD{},
+        RX{}, RY{}, R0{}, R1{},
+        R2{}, R3{}, R4{}, R5{},
+        R6{}, R7{}, R8{}, R9{},
+        RF{}, RI{}, RS{}, RZ{},
+        RE{}, RN{}, RV{}, RM{}
+    {}
 
     CPU::~CPU() {}
 
-    // Setup & Configuration //
-
-    void CPU::hookRAM(RAM* ram) {
-        this->_ram = ram;
-    }
-
-    void CPU::hookInstrReel(InstrReel* reel) {
-        this->_reel = reel;
-    }
-
-    constexpr u64 CPU::getFlag(u64 mask) {
-        if (!mask) return 0;
-#if __cplusplus >= 202002L
-        return (RF & mask) >> std::countr_zero(mask);
-#elif defined(SPIDER_COMPILER_GCC_LIKE)
-        return (RF & mask) >> __builtin_ctzll(mask);
-#elif defined(SPIDER_COMPILER_MSVC)
-        return (RF & mask) >> _BitScanForward64(mask);
-#else
-        // If you have reached this part,
-        // please come up with a better alternative.
-        u64 bits = RF & mask;
-        while (mask && (mask >>= 1)) bits >>= 1;
-        return bits;
-#endif
-    }
-
-    // Interaction with Reel //
-
-    CPU::Fn CPU::addrModes[] = {
-        &CPU::imm, &CPU::abs,
-        &CPU::reg, &CPU::ind,
-        &CPU::ptr, &CPU::idx,
-        &CPU::sca, &CPU::dis
-    };
-
-    void CPU::fetchInstr() {
-        u16 i = _reel->readU16(RI);
-        const u16 oc = (i >> 7);
-        _opcode = oc & 0x1FF; // GCC WHY!
-        _addrm = static_cast<u8>((i >> 2) & 0x1F);
-        _size = static_cast<u8>(i & 0x3);
-        RI += 2;
-    }
-
-    void CPU::fetchOperDst() {
-        // Move the operand ptrs
-        _alu = &ALU0;
-        _opers[1] = _opers[0];
-
-        // call specific addressing mode
-        (this->*(CPU::addrModes[_addrm & 0b111]))(); // mask added here too
-    }
-
-    void CPU::fetchOperSrc() {
-        // set ALU
-        _alu = &ALU1;
-
-        // call specific addressing mode
-        (this->*(CPU::addrModes[_addrm & 0b111]))(); // mask keeps index within 0-7
-
-        // modify the _addrm register
-        _addrm = static_cast<u8>((_addrm >> 3) & 0x1F);
-        _addrm++;
-    }
-
-
-    void CPU::execute() {
-        (this->*(CPU::instrMap[_opcode]))(); // no null check needed
-    }
-
-
-    // Addressing Modes //
-
-    /**
-     * Implied Addressing Mode
-     */
-    void CPU::imp() {
-        // Nothing //
-    }
-
-    /**
-     * Immediate Addressing Mode
-     */
-    void CPU::imm() {
-        _reel->loadRegister(RI, _size, _alu);
-        _opers[0] = _alu;
-        _post = &CPU::imp;
-        RI += 1 << _size;
-    }
-
-    /**
-     * Absolute Addressing Mode
-     */
-    void CPU::abs() {
-        // Load the actual ptr into the ALU
-        u8 mm = u8(getFlag(CPU::FLAG_MEMORY_MODE));
-        _reel->loadRegister(RI, mm, _alu);
-        RI += 1 << mm;
-
-        // read the memory from RAM
-        _store = _alu->_u64;
-        _ram->loadRegister(_store, _size, _alu);
-        _post = &CPU::psw;
-    }
-
-    /**
-     * Register Addressing Mode
-     */
-    void CPU::reg() { // NOT FINISHED
-        // Two consecutive registers can be declared
-        // Shift if the top part will become .reg too
-        u8 sh = ((_addrm & 0b11000) == 0b11000) * 4;
-        u8 use = 1 - (sh >> 2); // (sh / 4)
-
-        // get byte
-        u8 reg = (_reel->readU8(RI) >> sh) & 0xF;
-        _alu = &GPR[reg];
-        _opers[0] = _alu; // explicitly sets _opers[0] = _dst
-        RI += use;
-
-        // store no-op
-        _post = &CPU::imp;
-    }
-
-    /**
-     * Indrect Addressing Mode
-     */
-    void CPU::ind() {}
-
-    /**
-     * Pointer Addressing Mode
-     */
-    void CPU::ptr() {}
-
-    /**
-     * Indexed Addressing Mode
-     */
-    void CPU::idx() {}
-
-    /**
-     * Scaled Addressing Mode
-     */
-    void CPU::sca() {}
-
-    /**
-     * Displaced Addressing Mode
-     */
-    void CPU::dis() {}
-
-    /**
-     * Post Write Action
-     */
-    void CPU::psw() {}
-
 }
+/**
+ * @brief BRAD (0xF7) - Memory Integrity Checksum
+ * Escanea los primeros 256 bytes de memoria y valida contra una firma de seguridad.
+ * Implementado por Bradley Vergara Lara - Estancia 2026.
+ */
+void CPU::BRAD() {
+    u32 checksum = 0;
+    const u32 MAGIC_SIGNATURE = 0x504944; // Firma de integridad "PID"
+    
+    // Recorre la memoria base del sistema
+    for (u16 i = 0; i < 256; i++) {
+        checksum += memory.read8(i); 
+    }
+
+    // Si el checksum coincide, RA = 1 (OK), si no RA = 0 (Error)
+    RA = (checksum == MAGIC_SIGNATURE) ? 1 : 0;
+}

src/spider/runtime/cpu/CPU.hpp

@@ -15,6 +15,14 @@ namespace spider {
         static constexpr const u64 FLAG_INTERRUPT_REQUEST = 0b0000000000000000000000000000000000000000000000000000000000000100;
         static constexpr const u64 FLAG_EXCEPTION         = 0b0000000000000000000000000000000000000000000000000000000000001000;
         static constexpr const u64 FLAG_MEMORY_MODE       = 0b0000000000000000000000000000000000000000000000000000000000110000;
+        static constexpr const u64 FLAG_EXT_INT_DISABLE = 0b0000000000000000000000000000000000000000000000000000000010000000; // bit 7
+        static constexpr const u64 FLAG_EQUAL           = 0b0000000000000000000000000000000000000000000000000000010000000000; // bit 10
+        static constexpr const u64 FLAG_EPSILON_ENABLE  = 0b0000000000000000000000000000000000000000000000000001000000000000; // bit 12
+        static constexpr const u64 FLAG_HOTSWAP_SIGNAL  = 0b0000000000000000000000000000000000000000000000010000000000000000; // bit 16
+        static constexpr const u64 FLAG_USER_A          = 0b0000000000000000000000000000000000000000000100000000000000000000; // bit 20
+        static constexpr const u64 FLAG_USER_B          = 0b0000000000000000000000000000000000000000001000000000000000000000; // bit 21
+        static constexpr const u64 FLAG_USER_C          = 0b0000000000000000000000000000000000000000010000000000000000000000; // bit 22
+        static constexpr const u64 FLAG_USER_D          = 0b0000000000000000000000000000000000000000100000000000000000000000; // bit 23
 
     public: // Map of addressing modes & Instructions
 
@@ -83,11 +91,11 @@ namespace spider {
         /**
          * Pointer to the current RAM hooked into
          * the CPU.
-         *
+         * 
          * It is unproved whether having the RAM directly
          * into the CPU is better than not, or whether a
          * virtual BUS is better.
-         *
+         * 
          * Alas, this way we can have a CPU state switch
          * between memory and instruction banks.
          */
@@ -96,7 +104,7 @@ namespace spider {
         /**
          * Pointer to the current Instruction Reel
          * hooked into the CPU.
-         *
+         * 
          * Ditto as RAM.
          */
         InstrReel* _reel;
@@ -112,7 +120,7 @@ namespace spider {
         ~CPU();
 
     public:
-
+        
         CPU& operator=(const CPU& other) = default;
 
         CPU& operator=(CPU&& other) noexcept = default;
@@ -124,7 +132,7 @@ namespace spider {
         void hookInstrReel(InstrReel* reel);
 
         constexpr u64 getFlag(u64 mask);
-
+    
     public:
 
         /**
@@ -137,11 +145,11 @@ namespace spider {
          * Fetches the destination operand,
          * by calling the appropriate addressing
          * mode.
-         *
+         * 
          * Will read the bottom 3 bits.
          * For instructions with two operands,
          * call Src first.
-         *
+         * 
          * The internal variable _addrm
          * will not be modified. It will
          * be important when writing
@@ -151,14 +159,14 @@ namespace spider {
 
         /**
          * Fetches the source operand.
-         *
+         * 
          * For use in two operand instructions.
-         *
+         * 
          * Will read the bottom 3 bits. It will
          * then shift the _addrm 3 spaces
          * to ensure it aligns with the DST
          * next.
-         *
+         * 
          * Additionally, it will add 1 to _addrm
          * to account with
          */
@@ -176,7 +184,7 @@ namespace spider {
          * a large switch statement. Only suitable
          * for environments where the instruction
          * map is not possible.
-         *
+         * 
          * This has yet to be proved!!!
          */
         void executeSwLk();
@@ -197,32 +205,32 @@ namespace spider {
          * Absolute Addressing Mode
          */
         void abs();
-
+        
         /**
          * Register Addressing Mode
          */
         void reg();
-
+        
         /**
          * Indrect Addressing Mode
          */
         void ind();
-
+        
         /**
          * Pointer Addressing Mode
          */
         void ptr();
-
+        
         /**
          * Indexed Addressing Mode
          */
         void idx();
-
+        
         /**
          * Scaled Addressing Mode
          */
         void sca();
-
+        
         /**
          * Displaced Addressing Mode
          */
@@ -533,22 +541,22 @@ namespace spider {
 
         // [System] 0x040 — SFB: Store (User) Flag Bit
         //   Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
-        //   Operation:
+        //   Operation: 
         void SFB();
 
         // [System] 0x041 — LFB: Load (User) Flag Bit
         //   Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
-        //   Operation:
+        //   Operation: 
         void LFB();
 
         // [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true
         //   Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
-        //   Operation:
+        //   Operation: 
         void JUF();
 
         // [Branch] 0x043 — JUR: Jump to relative position, if user flag is true
         //   Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
-        //   Operation:
+        //   Operation: 
         void JUR();
 
         // [Memory] 0x044 — PUSH: Push to stack
@@ -593,7 +601,7 @@ namespace spider {
 
         // [Floating Point] 0x050 — FLI: Float Load Immediate
         //   Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
-        //   Operation:
+        //   Operation: 
         void FLI();
 
         // [Floating Point] 0x051 — FNEG: Float negate
@@ -808,77 +816,78 @@ namespace spider {
 
         // [Matrix] 0x080 — MADD: Matrix Addition
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void MADD();
 
         // [Matrix] 0x081 — MSUB: Matrix Subtraction
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void MSUB();
 
         // [Matrix] 0x082 — MMUL: Matrix Multiply
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void MMUL();
 
         // [Matrix] 0x083 — MINV: Matrix Inverse
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void MINV();
 
         // [Matrix] 0x084 — MTRA: Matrix Transpose
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void MTRA();
 
         // [Matrix] 0x085 — MDET: Matrix Determinant
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void MDET();
 
         // [Quaternion] 0x086 — QMKA: Quaternion Make from Angles
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void QMKA();
 
         // [Quaternion] 0x087 — QMUL: Quaternion Multiply
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void QMUL();
 
         // [SIMD] 0x08A — XADD: SIMD Addition
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void XADD();
 
         // [SIMD] 0x08B — XSUB: SIMD Subtract
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void XSUB();
 
         // [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void XAMA();
 
         // [SIMD] 0x08D — XMUL: SIMD Multiply
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void XMUL();
 
         // [SIMD] 0x08E — XDIV: SIMD Divide
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void XDIV();
 
         // [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory
         //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
-        //   Operation:
+        //   Operation: 
         void UPY();
 
-        //[Easter Egg] 0x0F1 - LLGS: Injects the custom 8x4 ASCII spider logo
-        // into RAM [0x80-0x9F] and signs Register RA with the "LLGS" hex literal.
-        void LLGS();
+        // [Easter Eggs] 0x0F6 — DGANT: "In kaaba Spider" (Yucatec Maya: My name is Spider)
+        //   Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
+        //   Operation: Writes "IN KAABA SPIDER" one char per GP register
+        void DGANT();
 
         // </pygen-target> //
 

src/spider/runtime/instr/InstrMap.cpp

@@ -276,12 +276,12 @@ CPU::Fn CPU::instrMap[] = {
     nullptr,                    // 0x0EE
     nullptr,                    // 0x0EF
     &CPU::UPY,                        // 0x0F0 — Will place "YUPI" in memory
-    &CPU::LLGS,                 // 0x0F1 — Spider ASCII art (LLGS easter egg)
+    nullptr,                    // 0x0F1
     nullptr,                    // 0x0F2
     nullptr,                    // 0x0F3
     nullptr,                    // 0x0F4
     nullptr,                    // 0x0F5
-    nullptr,                    // 0x0F6
+    &CPU::DGANT,                // 0x0F6
     nullptr,                    // 0x0F7
     nullptr,                    // 0x0F8
     nullptr,                    // 0x0F9
@@ -737,8 +737,6 @@ void CPU::executeSwLk() {
 
     // ── Easter Eggs ─────────────────────────────────
     case 0x0F0:  UPY();  break;
-    case 0x0F1:  LLGS();  break;
-
 
     default:
         break;

src/spider/runtime/instr/Instr_020-03F.cpp

@@ -178,20 +178,63 @@ namespace spider {
         // TODO: Implement JIF
     }
 
+    // ── 0x03C — JMR: Dst + Instruction Register -> Instruction Register ──
     void CPU::JMR() {
-        // TODO: Implement JMR
+        fetchOperDst();
+        i64 offset;
+        switch (_size) {
+            case 0b00: offset = static_cast<i64>(_dst->_i8);  break; // 1 byte
+            case 0b01: offset = static_cast<i64>(_dst->_i16); break; // 2 bytes
+            case 0b10: offset = static_cast<i64>(_dst->_i32); break; // 4 bytes
+            case 0b11: offset = _dst->_i64;                   break; // 8 bytes
+        }
+        RI = static_cast<u64>(static_cast<i64>(RI) + offset);
     }
 
+    // ── 0x03D — JER: Dst + Instruction Register -> Instruction Register IF Flags.EQ ──
     void CPU::JER() {
-        // TODO: Implement JER
+        fetchOperDst();
+        if (RF & CPU::FLAG_EQUAL) {
+            i64 offset;
+            switch (_size) {
+                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
+                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
+                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
+                case 0b11: offset = _dst->_i64;                   break;
+            }
+            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
+        }
     }
 
+    // ── 0x03E — JNR: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ ──
     void CPU::JNR() {
-        // TODO: Implement JNR
+        fetchOperDst();
+        if (!(RF & CPU::FLAG_EQUAL)) {
+            i64 offset;
+            switch (_size) {
+                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
+                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
+                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
+                case 0b11: offset = _dst->_i64;                   break;
+            }
+            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
+        }
     }
 
+    // ── 0x03F — JIR: Dst + Instruction Register -> Instruction Register IF Src ──
     void CPU::JIR() {
-        // TODO: Implement JIR
+        fetchOperSrc();
+        fetchOperDst();
+        if (_src->_u64 != 0) {
+            i64 offset;
+            switch (_size) {
+                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
+                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
+                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
+                case 0b11: offset = _dst->_i64;                   break;
+            }
+            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
+        }
     }
 
 }

src/spider/runtime/instr/Instr_040-05F.cpp

@@ -4,73 +4,195 @@
  */
 
 #include <spider/runtime/cpu/CPU.hpp>
+#include <spider/runtime/memory/RAM.hpp>
 #include <cmath> // provides std::fmod, std::fma and cast support
 
 
 namespace spider {
 
+    // ── 0x040 — SFB: Store (User) Flag Bit ──────────────────────────────
     void CPU::SFB() {
-        // TODO: Implement SFB
+        fetchOperSrc();
+        fetchOperDst();
+        u8 flag_idx = _dst->_u8 & 0x3;
+        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
+        if (_src->_u64 != 0) {
+            RF |= flag_bit;
+        } else {
+            RF &= ~flag_bit;
+        }
     }
 
+    // ── 0x041 — LFB: Load (User) Flag Bit ──────────────────────────────
     void CPU::LFB() {
-        // TODO: Implement LFB
+        fetchOperSrc();
+        fetchOperDst();
+        u8 flag_idx = _src->_u8 & 0x3;
+        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
+        _dst->_u64 = (RF & flag_bit) ? 1 : 0;
+        (this->*_post)();
     }
 
+    // ── 0x042 — JUF: Jump to absolute position, if user flag is true ────
     void CPU::JUF() {
-        // TODO: Implement JUF
+        fetchOperSrc();
+        fetchOperDst();
+        u8 flag_idx = _src->_u8 & 0x3;
+        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
+        if (RF & flag_bit) {
+            RI = _dst->_u64;
+        }
     }
 
+    // ── 0x043 — JUR: Jump to relative position, if user flag is true ────
     void CPU::JUR() {
-        // TODO: Implement JUR
+        fetchOperSrc();
+        fetchOperDst();
+        u8 flag_idx = _src->_u8 & 0x3;
+        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
+        if (RF & flag_bit) {
+            i64 offset;
+            switch (_size) {
+                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
+                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
+                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
+                case 0b11: offset = _dst->_i64;                   break;
+                default:   offset = 0;                             break;
+            }
+            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
+        }
     }
 
+    // ── 0x044 — PUSH: Dst -> pushed into stack ──────────────────────────
     void CPU::PUSH() {
-        // TODO: Implement PUSH
+        fetchOperDst();
+        u8 bytes = 1 << _size;
+        for (u8 i = 0; i < bytes; i++) {
+            _ram->at(RS + i) = (*_dst)[i];
+        }
+        RS += bytes;
     }
 
+    // ── 0x045 — POP: popped from stack -> Dst ───────────────────────────
     void CPU::POP() {
-        // TODO: Implement POP
+        fetchOperDst();
+        u8 bytes = 1 << _size;
+        RS -= bytes;
+        _ram->loadRegister(RS, _size, _dst);
+        (this->*_post)();
     }
 
+    // ── 0x046 — ALLOC: Dst -> heap ptr of size Dst ──────────────────────
     void CPU::ALLOC() {
-        // TODO: Implement ALLOC
+        fetchOperDst();
+        // TODO: Proper heap allocation with gap tracking.
+        _dst->_u64 = 0;
+        (this->*_post)();
     }
 
+    // ── 0x047 — HFREE: Frees heap ptr in Dst ────────────────────────────
     void CPU::HFREE() {
-        // TODO: Implement HFREE
+        fetchOperDst();
+        // TODO: Proper heap deallocation.
     }
 
+    // ── 0x04A — CALL: Performs a function call, step XX ──────────────────
     void CPU::CALL() {
-        // TODO: Implement CALL
+        fetchOperDst();
+        u64 target = _dst->_u64;
+
+        register_t rz_save;
+        rz_save._u64 = RZ;
+        for (u8 i = 0; i < 8; i++) {
+            _ram->at(RS + i) = rz_save[i];
+        }
+        RS += 8;
+
+        register_t ri_save;
+        ri_save._u64 = RI;
+        for (u8 i = 0; i < 8; i++) {
+            _ram->at(RS + i) = ri_save[i];
+        }
+        RS += 8;
+
+        RZ = RS;
+        RI = target;
     }
 
+    // ── 0x04B — RET: Undoes a function call, step XX ────────────────────
     void CPU::RET() {
-        // TODO: Implement RET
+        RS = RZ;
+
+        RS -= 8;
+        register_t ri_restore;
+        _ram->loadRegister(RS, 0b11, &ri_restore);
+        RI = ri_restore._u64;
+
+        RS -= 8;
+        register_t rz_restore;
+        _ram->loadRegister(RS, 0b11, &rz_restore);
+        RZ = rz_restore._u64;
     }
 
+    // ── 0x04C — EDI: bool( Dst ) -> Enable External Interrupts Bit ─────
     void CPU::EDI() {
-        // TODO: Implement EDI
+        fetchOperDst();
+        if (_dst->_u64 != 0) {
+            RF &= ~CPU::FLAG_EXT_INT_DISABLE;
+        } else {
+            RF |= CPU::FLAG_EXT_INT_DISABLE;
+        }
     }
 
+    // ── 0x04D — SHSS: bool( Dst ) -> Hot Swap Signal Bit ────────────────
     void CPU::SHSS() {
-        // TODO: Implement SHSS
+        fetchOperDst();
+        if (_dst->_u64 != 0) {
+            RF |= CPU::FLAG_HOTSWAP_SIGNAL;
+        } else {
+            RF &= ~CPU::FLAG_HOTSWAP_SIGNAL;
+        }
     }
 
+    // ── 0x050 — FLI: Float Load Immediate ───────────────────────────────
     void CPU::FLI() {
-        // TODO: Implement FLI
+        fetchOperDst();
+        (this->*_post)();
     }
 
+    // ── 0x051 — FNEG: - Dst -> Dst ──────────────────────────────────────
     void CPU::FNEG() {
-        // TODO: Implement FNEG
+        fetchOperDst();
+        switch (_size) {
+            case 0b10: _dst->_f32 = -_dst->_f32; break;
+            case 0b11: _dst->_f64 = -_dst->_f64; break;
+            default:                              break;
+        }
+        (this->*_post)();
     }
 
+    // ── 0x052 — FADD: Dst + Src -> Dst ──────────────────────────────────
     void CPU::FADD() {
-        // TODO: Implement FADD
+        fetchOperSrc();
+        fetchOperDst();
+        switch (_size) {
+            case 0b10: _dst->_f32 += _src->_f32; break;
+            case 0b11: _dst->_f64 += _src->_f64; break;
+            default:                              break;
+        }
+        (this->*_post)();
     }
 
+    // ── 0x053 — FSUB: Dst - Src -> Dst ──────────────────────────────────
     void CPU::FSUB() {
-        // TODO: Implement FSUB
+        fetchOperSrc();
+        fetchOperDst();
+        switch (_size) {
+            case 0b10: _dst->_f32 -= _src->_f32; break;
+            case 0b11: _dst->_f64 -= _src->_f64; break;
+            default:                              break;
+        }
+        (this->*_post)();
     }
 
     // ── 0x054 — FMUL: Float Multiplication ───────────────────────────────────

src/spider/runtime/instr/Instr_060-07F.cpp

@@ -70,63 +70,96 @@ namespace spider {
     }
 
     void CPU::D2I() {
-        // TODO: Implement D2I
+        fetchOperDst();
+        _dst->_u32 = static_cast<u32>(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::D2L() {
-        // TODO: Implement D2L
+        fetchOperDst();
+        _dst->_u64 = static_cast<u64>(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::SIN() {
-        // TODO: Implement SIN
+        fetchOperDst();
+        _dst->_f64 = std::sin(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::COS() {
-        // TODO: Implement COS
+        fetchOperDst();
+        _dst->_f64 = std::cos(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::TAN() {
-        // TODO: Implement TAN
+        fetchOperDst();
+        _dst->_f64 = std::tan(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::ASIN() {
-        // TODO: Implement ASIN
+        fetchOperDst();
+        _dst->_f64 = std::asin(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::ACOS() {
-        // TODO: Implement ACOS
+        fetchOperDst();
+        _dst->_f64 = std::acos(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::ATAN() {
-        // TODO: Implement ATAN
+        fetchOperDst();
+        _dst->_f64 = std::atan(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::ATAN2() {
-        // TODO: Implement ATAN2
+        fetchOperDst();
+        fetchOperSrc();
+        _dst->_f64 = std::atan2(_dst->_f64, _src->_f64);
+        (this->*_post)();
     }
 
     void CPU::EXP() {
-        // TODO: Implement EXP
+        fetchOperDst();
+        _dst->_f64 = std::exp(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::LOG() {
-        // TODO: Implement LOG
+        fetchOperDst();
+        _dst->_f64 = std::log(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::LOGAB() {
-        // TODO: Implement LOGAB
+        fetchOperDst();
+        fetchOperSrc();
+        _dst->_f64 = std::log(_dst->_f64) / std::log(_src->_f64);
+        (this->*_post)();
     }
 
     void CPU::POW() {
-        // TODO: Implement POW
+        fetchOperDst();
+        fetchOperSrc();
+        _dst->_f64 = std::pow(_dst->_f64, _src->_f64);
+        (this->*_post)();
     }
 
     void CPU::SQRT() {
-        // TODO: Implement SQRT
+        fetchOperDst();
+        _dst->_f64 = std::sqrt(_dst->_f64);
+        (this->*_post)();
     }
 
     void CPU::ROOT() {
-        // TODO: Implement ROOT
+        fetchOperDst();
+        fetchOperSrc();
+        _dst->_f64 = std::pow(_dst->_f64, 1.0 / _src->_f64);
     }
 
     void CPU::ADC() {

src/spider/runtime/instr/Instr_0E0-0FF.cpp

@@ -4,6 +4,7 @@
  */
 
 #include <spider/runtime/cpu/CPU.hpp>
+#include <spider/runtime/memory/RAM.hpp>
 
 namespace spider {
 
@@ -11,4 +12,44 @@ namespace spider {
         // TODO: Implement UPY
     }
 
+    // ── 0x0F6 — DGANT: "I'm SpiderLang" in a spider web ────────────
+    void CPU::DGANT() {
+        const char art[] =
+            R"(\  |  //)"
+            R"( \-+-// )"
+            R"( -- + --)"
+            R"( //-+-\ )"
+            R"(//  |  \)"
+            R"(        )"
+            R"(  I ' M )"
+            R"( SPIDER )"
+            R"(  LANG  )"
+            R"(        )"
+            R"(\  |  //)"
+            R"( \-+-// )"
+            R"(-- + -- )"
+            R"( /-+-\  )"
+            R"(/  |  \ )"
+            R"(   ||   )"
+            R"(   ||   )"
+            R"(   ||   )"
+            R"(\  |  / )"
+            R"( \-+-/  )"
+            R"(-- + -- )"
+            R"( /-+-\  )"
+            R"(/  |  \ )"
+            R"(   ||   )"
+            R"(   ||   )"
+            R"(   ||   )"
+            R"(\  |  / )"
+            R"( \-+-/  )"
+            R"(-- + -- )"
+            R"( /-+-\  )"
+            R"(/  |  \ )"
+            R"(   ||   )";
+        for (u16 i = 0; i < sizeof(art) - 1; i++) {
+            _ram->at(i) = static_cast<u8>(art[i]);
+        }
+    }
+
 }

src/spider/runtime/instr/Instr_LLGS.cpp

@@ -1,61 +0,0 @@
-/**
- * @brief LLGS — Easter egg by Arturo Balam (Data - 7A)
- *
- * Opcode: 0x0F1
- *
- * Writes a Spider ASCII art into RAM starting at address 0x00,
- * and loads the author signature into RA as a packed ASCII string.
- * This version matches the custom mechanical spider design
- * and is formatted to fit an 8-byte RAM viewer width.
- *
- * RAM layout after LLGS executes (8 characters per row, 4 rows total):
- * 0x00:  "// _ \\"   (Row 1)
- * 0x08:  "\\( )// "   (Row 2)
- * 0x10:  " //()\\ "   (Row 3)
- * 0x18:  " \\  // "   (Row 4)
- *
- * RA after execution: 0x4C4C475300000000ULL ("LLGS" in ASCII, zero-padded)
- * (L=0x4C, L=0x4C, G=0x47, S=0x53)
- */
-
-#include <spider/runtime/cpu/CPU.hpp>
-#include <spider/runtime/memory/RAM.hpp>
-
-namespace spider {
-
-    void CPU::LLGS() {
-
-        // -- Write Spider ASCII art into RAM ---------------------------------
-        // Padded with exact spaces to ensure it never wraps in an 8-byte viewer
-
-       // Row 0: "// _ \\ "
-        _ram->at(0x00) = '/';  _ram->at(0x01) = '/';
-        _ram->at(0x02) = ' ';  _ram->at(0x03) = '_';
-        _ram->at(0x04) = ' ';  _ram->at(0x05) = '\\';
-        _ram->at(0x06) = '\\'; _ram->at(0x07) = ' ';
-
-        // Row 1: "\\( )// "
-        _ram->at(0x08) = '\\'; _ram->at(0x09) = '\\';
-        _ram->at(0x0A) = '(';  _ram->at(0x0B) = ' ';
-        _ram->at(0x0C) = ')';  _ram->at(0x0D) = '/';
-        _ram->at(0x0E) = '/';  _ram->at(0x0F) = ' ';
-
-        // Row 2: " //()\\ "
-        _ram->at(0x10) = ' ';  _ram->at(0x11) = '/';
-        _ram->at(0x12) = '/';  _ram->at(0x13) = '(';
-        _ram->at(0x14) = ')';  _ram->at(0x15) = '\\';
-        _ram->at(0x16) = '\\'; _ram->at(0x17) = ' ';
-
-        // Row 3: " \\  // "
-        _ram->at(0x18) = ' ';  _ram->at(0x19) = '\\';
-        _ram->at(0x1A) = '\\'; _ram->at(0x1B) = ' ';
-        _ram->at(0x1C) = ' ';  _ram->at(0x1D) = '/';
-        _ram->at(0x1E) = '/';  _ram->at(0x1F) = ' ';
-
-        // -- Load mnemonic into RA ------------------------
-        // "LLGS" packed as ASCII bytes into RA
-        RA._u64 = 0x4C4C475300000000ULL;
-
-    }
-
-} // namespace spider