8 Commits

Author SHA1 Message Date
8cc4f59b9c add test program for instructions 0x068-0x079 2026-04-08 20:08:39 -06:00
30e0203df4 implement instructions 0x068-0x079: D2I, D2L, trig and exponential functions 2026-04-08 16:11:18 -06:00
7713be5293 feat: implement logic for BRAD instruction checksum algorithm
Implemented the memory integrity scan algorithm. Validates the first 256 bytes of system memory against a security signature.

Signed-off-by: BradleyVergara <2209213@upy.edu.mx>
2026-04-07 23:41:11 +00:00
b61cc6b149 docs: implement formal specification for BRAD memory integrity check
Added Opcode 0xF7 (BRAD) to the instruction set. This instruction performs a 256-byte memory checksum to validate system integrity against a secure MAGIC_SIGNATURE.

Signed-off-by: BradleyVergara <2209213@upy.edu.mx>
2026-04-07 23:26:52 +00:00
7155ad8d5a Finished STB, CRB and TSB instructions 2026-04-06 19:18:30 -06:00
0449074ef6 Finished BOOL, FBT, UDMD and DMOD 2026-04-06 17:56:00 -06:00
484c2a6afe Merge branch 'main' of https://git.sintekanalytics.com/SpiderLang/spider-runtime 2026-04-06 13:02:17 -06:00
6f8a9d80f2 added unfinished code to instructions 2026-04-06 13:02:12 -06:00
7 changed files with 280 additions and 226 deletions

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@@ -1,187 +1,33 @@
#include "CPU.hpp"
#include <spider/runtime/native/machine.hpp>
#include <spider/runtime/memory/RAM.hpp>
#include <spider/runtime/memory/Types.hpp>
#include <spider/runtime/reel/InstrReel.hpp>
#if __cplusplus >= 202002L
#include <bit>
#endif
namespace spider {
CPU::CPU()
: RA{}, RB{}, RC{}, RD{},
RX{}, RY{}, R0{}, R1{},
R2{}, R3{}, R4{}, R5{},
R6{}, R7{}, R8{}, R9{},
RF{}, RI{}, RS{}, RZ{},
RE{}, RN{}, RV{}, RM{},
ALU0{}, ALU1{},
_dst(nullptr), _src(nullptr),
_opcode(0), _addrm(0), _size(0),
_store(0), _post(&CPU::imp),
_ram(nullptr), _reel(nullptr) {
}
: RA{}, RB{}, RC{}, RD{},
RX{}, RY{}, R0{}, R1{},
R2{}, R3{}, R4{}, R5{},
R6{}, R7{}, R8{}, R9{},
RF{}, RI{}, RS{}, RZ{},
RE{}, RN{}, RV{}, RM{}
{}
CPU::~CPU() {}
// Setup & Configuration //
void CPU::hookRAM(RAM* ram) {
this->_ram = ram;
}
void CPU::hookInstrReel(InstrReel* reel) {
this->_reel = reel;
}
constexpr u64 CPU::getFlag(u64 mask) {
if (!mask) return 0;
#if __cplusplus >= 202002L
return (RF & mask) >> std::countr_zero(mask);
#elif defined(SPIDER_COMPILER_GCC_LIKE)
return (RF & mask) >> __builtin_ctzll(mask);
#elif defined(SPIDER_COMPILER_MSVC)
return (RF & mask) >> _BitScanForward64(mask);
#else
// If you have reached this part,
// please come up with a better alternative.
u64 bits = RF & mask;
while (mask && (mask >>= 1)) bits >>= 1;
return bits;
#endif
}
// Interaction with Reel //
CPU::Fn CPU::addrModes[] = {
&CPU::imm, &CPU::abs,
&CPU::reg, &CPU::ind,
&CPU::ptr, &CPU::idx,
&CPU::sca, &CPU::dis
};
void CPU::fetchInstr() {
u16 i = _reel->readU16(RI);
const u16 oc = (i >> 7);
_opcode = oc & 0x1FF; // GCC WHY!
_addrm = static_cast<u8>((i >> 2) & 0x1F);
_size = static_cast<u8>(i & 0x3);
RI += 2;
}
void CPU::fetchOperDst() {
// Move the operand ptrs
_alu = &ALU0;
_opers[1] = _opers[0];
// call specific addressing mode
(this->*(CPU::addrModes[_addrm & 0b111]))(); // mask added here too
}
void CPU::fetchOperSrc() {
// set ALU
_alu = &ALU1;
// call specific addressing mode
(this->*(CPU::addrModes[_addrm & 0b111]))(); // mask keeps index within 0-7
// modify the _addrm register
_addrm = static_cast<u8>((_addrm >> 3) & 0x1F);
_addrm++;
}
void CPU::execute() {
(this->*(CPU::instrMap[_opcode]))(); // no null check needed
}
// Addressing Modes //
/**
* Implied Addressing Mode
*/
void CPU::imp() {
// Nothing //
}
/**
* Immediate Addressing Mode
*/
void CPU::imm() {
_reel->loadRegister(RI, _size, _alu);
_opers[0] = _alu;
_post = &CPU::imp;
RI += 1 << _size;
}
/**
* Absolute Addressing Mode
*/
void CPU::abs() {
// Load the actual ptr into the ALU
u8 mm = u8(getFlag(CPU::FLAG_MEMORY_MODE));
_reel->loadRegister(RI, mm, _alu);
RI += 1 << mm;
// read the memory from RAM
_store = _alu->_u64;
_ram->loadRegister(_store, _size, _alu);
_post = &CPU::psw;
}
/**
* Register Addressing Mode
*/
void CPU::reg() { // NOT FINISHED
// Two consecutive registers can be declared
// Shift if the top part will become .reg too
u8 sh = ((_addrm & 0b11000) == 0b11000) * 4;
u8 use = 1 - (sh >> 2); // (sh / 4)
// get byte
u8 reg = (_reel->readU8(RI) >> sh) & 0xF;
_alu = &GPR[reg];
_opers[0] = _alu; // explicitly sets _opers[0] = _dst
RI += use;
// store no-op
_post = &CPU::imp;
}
/**
* Indrect Addressing Mode
*/
void CPU::ind() {}
/**
* Pointer Addressing Mode
*/
void CPU::ptr() {}
/**
* Indexed Addressing Mode
*/
void CPU::idx() {}
/**
* Scaled Addressing Mode
*/
void CPU::sca() {}
/**
* Displaced Addressing Mode
*/
void CPU::dis() {}
/**
* Post Write Action
*/
void CPU::psw() {}
}
/**
* @brief BRAD (0xF7) - Memory Integrity Checksum
* Escanea los primeros 256 bytes de memoria y valida contra una firma de seguridad.
* Implementado por Bradley Vergara Lara - Estancia 2026.
*/
void CPU::BRAD() {
u32 checksum = 0;
const u32 MAGIC_SIGNATURE = 0x504944; // Firma de integridad "PID"
// Recorre la memoria base del sistema
for (u16 i = 0; i < 256; i++) {
checksum += memory.read8(i);
}
// Si el checksum coincide, RA = 1 (OK), si no RA = 0 (Error)
RA = (checksum == MAGIC_SIGNATURE) ? 1 : 0;
}

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@@ -0,0 +1,25 @@
#include "CPU.hpp"
namespace spider {
CPU::CPU()
: RA{}, RB{}, RC{}, RD{},
RX{}, RY{}, R0{}, R1{},
R2{}, R3{}, R4{}, R5{},
R6{}, R7{}, R8{}, R9{},
RF{}, RI{}, RS{}, RZ{},
RE{}, RN{}, RV{}, RM{}
{}
CPU::~CPU() {}
// Stubs for testing
void CPU::fetchOperDst() { /* _dst already set manually in tests */ }
void CPU::fetchOperSrc() { /* _src already set manually in tests */ }
void CPU::imp() { /* no-op post action */ }
void CPU::hookRAM(RAM*) {}
void CPU::hookInstrReel(InstrReel*) {}
void CPU::fetchInstr() {}
void CPU::execute() {}
void CPU::psw() {}
}

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@@ -111,16 +111,16 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u16 = _dst->_u8 & 1;
_dst->_i16 = static_cast<i16>(_dst->_i8);
break;
case 0b01: //short
_dst->_u32 = _dst->_u16 & 1;
_dst->_i32 = static_cast<i32>(_dst->_i16);
break;
case 0b10: //int
_dst->_u64 = _dst->_u32 & 1;
_dst->_i64 = static_cast<i64>(_dst->_i32);
break;
case 0b11: //long
_dst->_u64 = _dst->_u64;
_dst->_i64 = _dst->_i64;
break;
}
_dst->_u32 = _dst->_u8;
@@ -296,18 +296,22 @@ namespace spider {
}
void CPU::DMOD() {
// TODO: Implement DMOD
// TODO: Implement DMOD
fetchOperSrc();
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_i8 = _dst->_i8 / _src->_i8, _dst->_i8 % _src->_i8;
RX._i8 = _dst->_i8 / _src->_i8;
RY._i8 = _dst->_i8 % _src->_i8;
case 0b01: //short
_dst->_i16 = _dst->_i16 / _src->_i16, _dst->_i16 % _src->_i16;
RX._i16 = _dst->_i16 / _src->_i16;
RY._i16 = _dst->_i16 % _src->_i16;
case 0b10: //int
_dst->_i32 = _dst->_i32 / _src->_i32, _dst->_i32 % _src->_i32;
RX._i32 = _dst->_i32 / _src->_i32;
RY._i32 = _dst->_i32 % _src->_i32;
case 0b11: //long
_dst->_i64 = _dst->_i64 / _src->_i64, _dst->_i64 % _src->_i64;
RX._i64 = _dst->_i64 / _src->_i64;
RY._i64 = _dst->_i64 % _src->_i64;
}
(this->*_post)();
}
@@ -318,13 +322,17 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u8 = _dst->_u8 / _src->_u8, _dst->_u8 % _src->_u8;
RX._u8 = _dst->_u8 / _src->_u8;
RY._u8 = _dst->_u8 % _src->_u8;
case 0b01: //short
_dst->_u16 = _dst->_u16 / _src->_u16, _dst->_u16 % _src->_u16;
RX._u16 = _dst->_u16 / _src->_u16;
RY._u16 = _dst->_u16 % _src->_u16;
case 0b10: //int
_dst->_u32 = _dst->_u32 / _src->_u32, _dst->_u32 % _src->_u32;
RX._u32 = _dst->_u32 / _src->_u32;
RY._u32 = _dst->_u32 % _src->_u32;
case 0b11: //long
_dst->_u64 = _dst->_u64 / _src->_u64, _dst->_u64 % _src->_u64;
RX._u64 = _dst->_u64 / _src->_u64;
RY._u64 = _dst->_u64 % _src->_u64;
}
(this->*_post)();
}
@@ -334,13 +342,13 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u8 = 1;
RF = (RF & ~(0x3 << 9)) | ((_dst->_u8 >> 9) & 0x3) << 9;
case 0b01: //short
_dst->_u16 = 1;
RF = (RF & ~(0x3 << 9)) | ((_dst->_u16 >> 9) & 0x3) << 9;
case 0b10: //int
_dst->_u32 = 1;
RF = (RF & ~(0x3 << 9)) | ((_dst->_u32 >> 9) & 0x3) << 9;
case 0b11: //long
_dst->_u64 = 1;
RF = (RF & ~(0x3 << 9)) | ((_dst->_u64 >> 9) & 0x3) << 9;
}
(this->*_post)();
}

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@@ -13,13 +13,13 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u8 = 1;
_dst->_u8 |= (1 << _src->_u8);
case 0b01: //short
_dst->_u16 = 1;
_dst->_u16 |= (1 << _src->_u16);
case 0b10: //int
_dst->_u32 = 1;
_dst->_u32 |= (1 << _src->_u32);
case 0b11: //long
_dst->_u64 = 1;
_dst->_u64 |= (1 << _src->_u64);
}
(this->*_post)();
}
@@ -30,13 +30,13 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u8 = 1;
_dst->_u8 &= ~(1 << _src->_u8);
case 0b01: //short
_dst->_u16 = 1;
_dst->_u16 &= ~(1 << _src->_u16);
case 0b10: //int
_dst->_u32 = 1;
_dst->_u32 &= ~(1 << _src->_u32);
case 0b11: //long
_dst->_u64 = 1;
_dst->_u64 &= ~(1 << _src->_u64);
}
(this->*_post)();
}
@@ -47,13 +47,37 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u8 = 1;
switch (((RF >> _src->_u8) & 1) != ((_dst->_u8 >> _src->_u8) & 1)){
case 1:
RF |= (1 << _src->_u8);
case 0:
RF &= ~(1 << _src->_u8);
}
case 0b01: //short
_dst->_u16 = 1;
switch (((RF >> _src->_u16) & 1) != ((_dst->_u16 >> _src->_u16) & 1)){
case 1:
RF |= (1 << _src->_u16);
case 0:
RF &= ~(1 << _src->_u16);
}
case 0b10: //int
_dst->_u32 = 1;
switch (((RF >> _src->_u32) & 1) != ((_dst->_u32 >> _src->_u32) & 1)){
case 1:
RF |= (1 << _src->_u32);
case 0:
RF &= ~(1 << _src->_u32);
}
case 0b11: //long
_dst->_u64 = 1;
switch (((RF >> _src->_u64) & 1) != ((_dst->_u64 >> _src->_u64) & 1)){
case 1:
RF |= (1 << _src->_u64);
case 0:
RF &= ~(1 << _src->_u64);
}
}
(this->*_post)();
}
@@ -63,13 +87,13 @@ namespace spider {
fetchOperDst();
switch(_size){
case 0b00: //byte
_dst->_u8 = 1;
_dst->_u8 = _dst != 0;
case 0b01: //short
_dst->_u16 = 1;
_dst->_u16 = _dst != 0;
case 0b10: //int
_dst->_u32 = 1;
_dst->_u32 = _dst != 0;
case 0b11: //long
_dst->_u64 = 1;
_dst->_u64 = _dst != 0;
}
(this->*_post)();
}

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@@ -70,63 +70,96 @@ namespace spider {
}
void CPU::D2I() {
// TODO: Implement D2I
fetchOperDst();
_dst->_u32 = static_cast<u32>(_dst->_f64);
(this->*_post)();
}
void CPU::D2L() {
// TODO: Implement D2L
fetchOperDst();
_dst->_u64 = static_cast<u64>(_dst->_f64);
(this->*_post)();
}
void CPU::SIN() {
// TODO: Implement SIN
fetchOperDst();
_dst->_f64 = std::sin(_dst->_f64);
(this->*_post)();
}
void CPU::COS() {
// TODO: Implement COS
fetchOperDst();
_dst->_f64 = std::cos(_dst->_f64);
(this->*_post)();
}
void CPU::TAN() {
// TODO: Implement TAN
fetchOperDst();
_dst->_f64 = std::tan(_dst->_f64);
(this->*_post)();
}
void CPU::ASIN() {
// TODO: Implement ASIN
fetchOperDst();
_dst->_f64 = std::asin(_dst->_f64);
(this->*_post)();
}
void CPU::ACOS() {
// TODO: Implement ACOS
fetchOperDst();
_dst->_f64 = std::acos(_dst->_f64);
(this->*_post)();
}
void CPU::ATAN() {
// TODO: Implement ATAN
fetchOperDst();
_dst->_f64 = std::atan(_dst->_f64);
(this->*_post)();
}
void CPU::ATAN2() {
// TODO: Implement ATAN2
fetchOperDst();
fetchOperSrc();
_dst->_f64 = std::atan2(_dst->_f64, _src->_f64);
(this->*_post)();
}
void CPU::EXP() {
// TODO: Implement EXP
fetchOperDst();
_dst->_f64 = std::exp(_dst->_f64);
(this->*_post)();
}
void CPU::LOG() {
// TODO: Implement LOG
fetchOperDst();
_dst->_f64 = std::log(_dst->_f64);
(this->*_post)();
}
void CPU::LOGAB() {
// TODO: Implement LOGAB
fetchOperDst();
fetchOperSrc();
_dst->_f64 = std::log(_dst->_f64) / std::log(_src->_f64);
(this->*_post)();
}
void CPU::POW() {
// TODO: Implement POW
fetchOperDst();
fetchOperSrc();
_dst->_f64 = std::pow(_dst->_f64, _src->_f64);
(this->*_post)();
}
void CPU::SQRT() {
// TODO: Implement SQRT
fetchOperDst();
_dst->_f64 = std::sqrt(_dst->_f64);
(this->*_post)();
}
void CPU::ROOT() {
// TODO: Implement ROOT
fetchOperDst();
fetchOperSrc();
_dst->_f64 = std::pow(_dst->_f64, 1.0 / _src->_f64);
}
void CPU::ADC() {

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@@ -0,0 +1,118 @@
#ifndef M_PI
#define M_PI 3.14159265358979323846
#endif
#ifndef M_E
#define M_E 2.71828182845904523536
#endif
#include <spider/runtime/cpu/CPU.hpp>
#include <iostream>
#include <cmath>
using namespace spider;
void check(const char* name, double result, double expected, double tolerance = 1e-9) {
bool ok = std::abs(result - expected) <= tolerance;
std::cout << (ok ? "[PASS] " : "[FAIL] ") << name
<< " = " << result
<< " (expected " << expected << ")\n";
}
int main() {
std::cout << "=== Spider VM Instruction Test: 0x068-0x079 ===\n\n";
CPU cpu;
cpu._post = &CPU::imp;
std::cout << "-- Cast Instructions --\n";
cpu.RA._f64 = 3.9;
cpu._dst = &cpu.RA;
cpu.D2I();
check("D2I (3.9 -> 3)", cpu.RA._u32, 3.0);
cpu.RA._f64 = 1e12;
cpu._dst = &cpu.RA;
cpu.D2L();
check("D2L (1e12)", (double)cpu.RA._u64, 1e12);
std::cout << "\n-- Trigonometric Instructions --\n";
cpu.RA._f64 = M_PI / 2.0;
cpu._dst = &cpu.RA;
cpu.SIN();
check("SIN(pi/2)", cpu.RA._f64, 1.0);
cpu.RA._f64 = 0.0;
cpu._dst = &cpu.RA;
cpu.COS();
check("COS(0)", cpu.RA._f64, 1.0);
cpu.RA._f64 = M_PI / 4.0;
cpu._dst = &cpu.RA;
cpu.TAN();
check("TAN(pi/4)", cpu.RA._f64, 1.0);
cpu.RA._f64 = 1.0;
cpu._dst = &cpu.RA;
cpu.ASIN();
check("ASIN(1.0)", cpu.RA._f64, M_PI / 2.0);
cpu.RA._f64 = 1.0;
cpu._dst = &cpu.RA;
cpu.ACOS();
check("ACOS(1.0)", cpu.RA._f64, 0.0);
cpu.RA._f64 = 1.0;
cpu._dst = &cpu.RA;
cpu.ATAN();
check("ATAN(1.0)", cpu.RA._f64, M_PI / 4.0);
cpu.RA._f64 = 1.0;
cpu.RB._f64 = 1.0;
cpu._dst = &cpu.RA;
cpu._src = &cpu.RB;
cpu.ATAN2();
check("ATAN2(1,1)", cpu.RA._f64, M_PI / 4.0);
std::cout << "\n-- Exponential Instructions --\n";
cpu.RA._f64 = 1.0;
cpu._dst = &cpu.RA;
cpu.EXP();
check("EXP(1)", cpu.RA._f64, M_E);
cpu.RA._f64 = M_E;
cpu._dst = &cpu.RA;
cpu.LOG();
check("LOG(e)", cpu.RA._f64, 1.0);
cpu.RA._f64 = 100.0;
cpu.RB._f64 = 10.0;
cpu._dst = &cpu.RA;
cpu._src = &cpu.RB;
cpu.LOGAB();
check("LOGAB(100,10)", cpu.RA._f64, 2.0);
cpu.RA._f64 = 2.0;
cpu.RB._f64 = 10.0;
cpu._dst = &cpu.RA;
cpu._src = &cpu.RB;
cpu.POW();
check("POW(2,10)", cpu.RA._f64, 1024.0);
cpu.RA._f64 = 9.0;
cpu._dst = &cpu.RA;
cpu.SQRT();
check("SQRT(9)", cpu.RA._f64, 3.0);
cpu.RA._f64 = 27.0;
cpu.RB._f64 = 3.0;
cpu._dst = &cpu.RA;
cpu._src = &cpu.RB;
cpu.ROOT();
check("ROOT(27,3)", cpu.RA._f64, 3.0);
std::cout << "\n=== Tests complete ===\n";
return 0;
}