136 lines
5.8 KiB
Markdown
136 lines
5.8 KiB
Markdown
# Blog Entry #2 — Registers, Addressing Modes & Type Size Modifiers
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In this second entry I will cover three fundamental concepts of the
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Spider Virtual Machine: the register table, addressing modes, and
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type size modifiers. These three systems work together to define how
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every single instruction in Spider operates.
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---
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## Registers
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The Spider VM provides two categories of registers.
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**General Purpose Registers (16 total)** are directly accessible from
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instructions using addressing modes. They can hold either integers or
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floats depending on the instruction being executed.
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The 16 GP registers have defined roles by convention:
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- `RA` — First argument and return value of a function
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- `RB`, `RC`, `RD` — Second, third and fourth arguments
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- `RX`, `RY` — Free auxiliary registers with no rules
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- `R0`–`R3` — Caller-saved: the called function may overwrite them
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- `R4`–`R7` — Callee-saved: the called function must restore them
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- `R8`, `R9` — Fifth and sixth function arguments
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**System Registers (8 total)** cannot be accessed directly by addressing
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modes. They require dedicated instructions to read or modify them, and
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they are always integers.
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The most important system registers are:
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- `RF` — Flag Register: holds the full state of the VM in 64 bits
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- `RI` — Instruction Register: points to the current instruction (program counter)
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- `RS` — Stack Register: tracks the current top of the stack
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- `RZ` — Stack Base Register: base reference for the current function frame
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- `RE` — Exception Register: holds the address of the active exception handler
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- `RV` — Interrupt Vector Register: used for both internal and external interrupts
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- `RM` — Memory Register: total RAM available to the VM
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One of Spider's core design decisions is to prioritize registers over
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the stack. Since registers are always available and fast to access,
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a well-written Spider program can run with minimal stack usage.
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This is especially important on constrained hardware like the ATmega328p,
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which only has 2KB of RAM.
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---
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## Addressing Modes
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Each instruction in Spider operates on parameters. An addressing mode
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defines **how to interpret** those parameters. The same instruction can
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behave very differently depending on the mode.
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Spider has 8 addressing modes:
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| Mode | Syntax | Meaning |
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|-----------|-------------------|------------------------------------------------------|
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| Implied | (none) | No parameter needed, operand is implicit |
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| Immediate | `42i` | The value is a literal constant |
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| Absolute | `0x1000i` | The value is a fixed memory address |
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| Register | `RA` | The value is stored in a register |
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| Indirect | `[0x1000i]` | Go to that address and use what's stored there |
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| Pointer | `[RA]` | The register holds a memory address, follow it |
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| Indexed | `[RA + 8i]` | Base register plus a constant offset |
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| Scaled | `[RA + RB * 4i]` | Base register plus scaled index register |
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| Displaced | `[RA + RB*4i+2i]` | Full address calculation with two registers |
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Addressing modes are encoded in 5 bits inside each 2-byte instruction.
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When an instruction has two parameters, those 5 bits are split: 2 bits
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for the first parameter and 3 bits for the second.
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A modifier suffix is used in assembly syntax to specify the mode explicitly:
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`.imp`, `.imm`, `.abs`, `.reg`, `.ind`, `.ptr`, `.idx`, `.sca`, `.dis`
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For example:
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```
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MOV.reg RA, RB ; move value from RB into RA using registers
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MOV.ptr RA, [RB] ; move value from address stored in RB into RA
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MOV.idx RA, [RB + 8i] ; move value from address RB+8 into RA
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```
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---
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## Type Size Modifiers
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Every instruction in Spider also carries a **type size modifier** encoded
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in the last 2 bits of the 2-byte instruction header. This tells the VM
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how many bytes to read or write when executing the instruction.
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| Type | Modifier | Size |
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|--------|----------|--------|
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| Byte | `.B` | 1 byte |
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| Short | `.S` | 2 bytes|
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| Int | `.I` | 4 bytes|
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| Long | `.L` | 8 bytes|
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| Float | `.F` | 4 bytes|
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| Double | `.D` | 8 bytes|
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The type modifier applies to the **entire instruction**, meaning both
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operands must be congruent. You cannot mix sizes in a single instruction.
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This system is directly tied to Spider's philosophy of **strong typing**:
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the programmer always knows exactly how much memory an operation consumes.
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There are no hidden conversions or surprises.
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Two important behaviors to understand:
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**Reading a smaller size** ignores the top bits of the value. For example,
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reading a register containing `0x12345678` with `.B` gives you `0x78`.
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**Writing a smaller size** only modifies the lower bytes and leaves the
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top bits untouched. Writing `0xAB` with `.B` into that same register
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gives you `0x123456AB`.
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A complete instruction combining all three systems looks like this:
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```
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MOV.I.reg RA, RB ; move a 4-byte integer from RB into RA
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MOV.B.ptr RA, [RB] ; move 1 byte from the address in RB into RA
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ADD.L.idx RA, [RB + 8i] ; add 8-byte value at address RB+8 into RA
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```
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---
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## How these three systems connect
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These three concepts are not independent. Every instruction in Spider
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uses all three simultaneously:
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- The **op code** (9 bits) says what to do
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- The **addressing mode** (5 bits) says where the data is
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- The **type modifier** (2 bits) says how big the data is
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Together they fit in exactly 2 bytes per instruction, followed by the
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actual parameter data. This compact design is what makes Spider efficient
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enough to run on microcontrollers with very limited memory. |