453 lines
15 KiB
C++
453 lines
15 KiB
C++
/**
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* @brief AUTO-GENERATED by pygen.ipynb BUT editable by hand!
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*
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*/
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#include <spider/runtime/cpu/CPU.hpp>
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namespace spider {
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void CPU::STB() {
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// TODO: Implement STB
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fetchOperSrc();
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fetchOperDst();
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switch(_size){
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case 0b00: //byte
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_dst->_u8 |= (1 << _src->_u8);
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case 0b01: //short
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_dst->_u16 |= (1 << _src->_u16);
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case 0b10: //int
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_dst->_u32 |= (1 << _src->_u32);
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case 0b11: //long
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_dst->_u64 |= (1 << _src->_u64);
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}
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(this->*_post)();
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}
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void CPU::CRB() {
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// TODO: Implement CRB
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fetchOperSrc();
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fetchOperDst();
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switch(_size){
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case 0b00: //byte
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_dst->_u8 &= ~(1 << _src->_u8);
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case 0b01: //short
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_dst->_u16 &= ~(1 << _src->_u16);
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case 0b10: //int
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_dst->_u32 &= ~(1 << _src->_u32);
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case 0b11: //long
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_dst->_u64 &= ~(1 << _src->_u64);
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}
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(this->*_post)();
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}
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void CPU::TSB() {
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// TODO: Implement TSB
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fetchOperSrc();
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fetchOperDst();
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switch(_size){
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case 0b00: //byte
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switch (((RF >> _src->_u8) & 1) != ((_dst->_u8 >> _src->_u8) & 1)){
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case 1:
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RF |= (1 << _src->_u8);
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case 0:
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RF &= ~(1 << _src->_u8);
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}
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case 0b01: //short
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switch (((RF >> _src->_u16) & 1) != ((_dst->_u16 >> _src->_u16) & 1)){
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case 1:
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RF |= (1 << _src->_u16);
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case 0:
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RF &= ~(1 << _src->_u16);
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}
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case 0b10: //int
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switch (((RF >> _src->_u32) & 1) != ((_dst->_u32 >> _src->_u32) & 1)){
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case 1:
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RF |= (1 << _src->_u32);
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case 0:
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RF &= ~(1 << _src->_u32);
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}
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case 0b11: //long
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switch (((RF >> _src->_u64) & 1) != ((_dst->_u64 >> _src->_u64) & 1)){
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case 1:
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RF |= (1 << _src->_u64);
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case 0:
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RF &= ~(1 << _src->_u64);
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}
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}
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(this->*_post)();
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}
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void CPU::BOOL() {
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// TODO: Implement BOOL
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fetchOperDst();
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switch(_size){
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case 0b00: //byte
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_dst->_u8 = _dst != 0;
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case 0b01: //short
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_dst->_u16 = _dst != 0;
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case 0b10: //int
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_dst->_u32 = _dst != 0;
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case 0b11: //long
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_dst->_u64 = _dst != 0;
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}
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(this->*_post)();
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}
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// ── 0x024 — NOT: Tests Dst == 0, updates Equal Flag ──
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void CPU::NOT() {
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fetchOperDst();
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bool isZero = false;
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switch(_size) {
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case 0b00: isZero = (_dst->_u8 == 0); break;
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case 0b01: isZero = (_dst->_u16 == 0); break;
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case 0b10: isZero = (_dst->_u32 == 0); break;
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case 0b11: isZero = (_dst->_u64 == 0); break;
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}
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if (isZero) {
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RF |= CPU::FLAG_EQUAL; // Si es 0, el resultado de !0 es true (1), actualizamos bandera
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// Dependiendo de la implementación de BOOL, podrías querer guardar el resultado en Dst
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_dst->_u64 = 1;
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} else {
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RF &= ~CPU::FLAG_EQUAL;
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_dst->_u64 = 0;
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}
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(this->*_post)();
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}
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// ── 0x025 — AND
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void CPU::AND() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 &= _src->_u8; break;
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case 0b01: _dst->_u16 &= _src->_u16; break;
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case 0b10: _dst->_u32 &= _src->_u32; break;
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case 0b11: _dst->_u64 &= _src->_u64; break;
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}
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(this->*_post)();
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}
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// ── 0x026 — OR
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void CPU::OR() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 |= _src->_u8; break;
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case 0b01: _dst->_u16 |= _src->_u16; break;
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case 0b10: _dst->_u32 |= _src->_u32; break;
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case 0b11: _dst->_u64 |= _src->_u64; break;
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}
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(this->*_post)();
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}
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// ── 0x027 — XOR
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void CPU::XOR() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 ^= _src->_u8; break;
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case 0b01: _dst->_u16 ^= _src->_u16; break;
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case 0b10: _dst->_u32 ^= _src->_u32; break;
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case 0b11: _dst->_u64 ^= _src->_u64; break;
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}
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(this->*_post)();
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}
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// ── 0x028 — SHL
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void CPU::SHL() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 <<= _src->_u8; break;
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case 0b01: _dst->_u16 <<= _src->_u16; break;
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case 0b10: _dst->_u32 <<= _src->_u32; break;
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case 0b11: _dst->_u64 <<= _src->_u64; break;
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}
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(this->*_post)();
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}
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// ── 0x029 — SHR
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void CPU::SHR() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 >>= _src->_u8; break;
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case 0b01: _dst->_u16 >>= _src->_u16; break;
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case 0b10: _dst->_u32 >>= _src->_u32; break;
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case 0b11: _dst->_u64 >>= _src->_u64; break;
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}
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(this->*_post)();
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}
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// ── 0x02A — SSR
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void CPU::SSR() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_i8 >>= _src->_u8; break;
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case 0b01: _dst->_i16 >>= _src->_u8; break;
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case 0b10: _dst->_i32 >>= _src->_u8; break;
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case 0b11: _dst->_i64 >>= _src->_u8; break;
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}
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(this->*_post)();
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}
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// ── 0x02B — ROL: Rotate Left ──
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void CPU::ROL() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 = (_dst->_u8 << _src->_u8) | (_dst->_u8 >> (8 - _src->_u8)); break;
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case 0b01: _dst->_u16 = (_dst->_u16 << _src->_u8) | (_dst->_u16 >> (16 - _src->_u8)); break;
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case 0b10: _dst->_u32 = (_dst->_u32 << _src->_u8) | (_dst->_u32 >> (32 - _src->_u8)); break;
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case 0b11: _dst->_u64 = (_dst->_u64 << _src->_u8) | (_dst->_u64 >> (64 - _src->_u8)); break;
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}
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(this->*_post)();
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}
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// ── 0x02C — ROR: Rotate Right ──
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void CPU::ROR() {
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fetchOperSrc();
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 = (_dst->_u8 >> _src->_u8) | (_dst->_u8 << (8 - _src->_u8)); break;
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case 0b01: _dst->_u16 = (_dst->_u16 >> _src->_u8) | (_dst->_u16 << (16 - _src->_u8)); break;
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case 0b10: _dst->_u32 = (_dst->_u32 >> _src->_u8) | (_dst->_u32 << (32 - _src->_u8)); break;
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case 0b11: _dst->_u64 = (_dst->_u64 >> _src->_u8) | (_dst->_u64 << (64 - _src->_u8)); break;
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}
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(this->*_post)();
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}
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// ── 0x02D — CNT: Counts bits (# of 1's into Dst) ──
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void CPU::CNT() {
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fetchOperDst();
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switch(_size) {
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case 0b00: _dst->_u8 = __builtin_popcount(_dst->_u8); break;
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case 0b01: _dst->_u16 = __builtin_popcount(_dst->_u16); break;
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case 0b10: _dst->_u32 = __builtin_popcount(_dst->_u32); break;
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case 0b11: _dst->_u64 = __builtin_popcountll(_dst->_u64); break;
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}
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(this->*_post)();
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}
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// ── 0x030 — EQ: Dst == Src into Dst ──
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void CPU::EQ() {
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fetchOperSrc();
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fetchOperDst();
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bool res = false;
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switch(_size) {
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case 0b00: res = (_dst->_u8 == _src->_u8); break;
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case 0b01: res = (_dst->_u16 == _src->_u16); break;
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case 0b10: res = (_dst->_u32 == _src->_u32); break;
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case 0b11: res = (_dst->_u64 == _src->_u64); break;
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}
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_dst->_u64 = res ? 1 : 0;
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(this->*_post)();
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}
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// ── 0x031 — NE: Dst != Src into Dst ──
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void CPU::NE() {
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fetchOperSrc();
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fetchOperDst();
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bool res = false;
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switch(_size) {
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case 0b00: res = (_dst->_u8 != _src->_u8); break;
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case 0b01: res = (_dst->_u16 != _src->_u16); break;
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case 0b10: res = (_dst->_u32 != _src->_u32); break;
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case 0b11: res = (_dst->_u64 != _src->_u64); break;
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}
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_dst->_u64 = res ? 1 : 0;
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(this->*_post)();
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}
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// ── 0x032 — GT: Dst > Src into Dst ──
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void CPU::GT() {
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fetchOperSrc();
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fetchOperDst();
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bool res = false;
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switch(_size) {
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case 0b00: res = (_dst->_i8 > _src->_i8); break;
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case 0b01: res = (_dst->_i16 > _src->_i16); break;
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case 0b10: res = (_dst->_i32 > _src->_i32); break;
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case 0b11: res = (_dst->_i64 > _src->_i64); break;
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}
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_dst->_u64 = res ? 1 : 0;
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(this->*_post)();
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}
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// ── 0x033 — GE: Dst >= Src into Dst ──
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void CPU::GE() {
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fetchOperSrc();
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fetchOperDst();
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bool res = false;
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switch(_size) {
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case 0b00: res = (_dst->_i8 >= _src->_i8); break;
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case 0b01: res = (_dst->_i16 >= _src->_i16); break;
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case 0b10: res = (_dst->_i32 >= _src->_i32); break;
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case 0b11: res = (_dst->_i64 >= _src->_i64); break;
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}
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_dst->_u64 = res ? 1 : 0;
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(this->*_post)();
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}
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// ── 0x034 — LT: Dst < Src into Dst ──
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void CPU::LT() {
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fetchOperSrc();
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fetchOperDst();
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bool res = false;
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switch(_size) {
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case 0b00: res = (_dst->_i8 < _src->_i8); break;
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case 0b01: res = (_dst->_i16 < _src->_i16); break;
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case 0b10: res = (_dst->_i32 < _src->_i32); break;
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case 0b11: res = (_dst->_i64 < _src->_i64); break;
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}
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_dst->_u64 = res ? 1 : 0;
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(this->*_post)();
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}
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// ── 0x035 — LE: Dst <= Src into Dst ──
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void CPU::LE() {
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fetchOperSrc();
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fetchOperDst();
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bool res = false;
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switch(_size) {
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case 0b00: res = (_dst->_i8 <= _src->_i8); break;
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case 0b01: res = (_dst->_i16 <= _src->_i16); break;
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case 0b10: res = (_dst->_i32 <= _src->_i32); break;
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case 0b11: res = (_dst->_i64 <= _src->_i64); break;
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}
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_dst->_u64 = res ? 1 : 0;
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(this->*_post)();
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}
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// ── 0x038 — JMP: Dst -> Instruction Register (PC) ──
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// The IR adds 1 at the end, so we subtract 1 to compensate.
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void CPU::JMP() {
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fetchOperDst();
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u64 target;
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switch(_size) {
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case 0b00: target = static_cast<u64>(_dst->_u8); break;
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case 0b01: target = static_cast<u64>(_dst->_u16); break;
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case 0b10: target = static_cast<u64>(_dst->_u32); break;
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case 0b11: target = _dst->_u64; break;
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}
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RI = target - 1;
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(this->*_post)();
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}
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// ── 0x039 — JEQ: Jump if EQ flag is set ──
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void CPU::JEQ() {
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fetchOperDst();
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if (RF & CPU::FLAG_EQUAL) {
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u64 target;
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switch(_size) {
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case 0b00: target = static_cast<u64>(_dst->_u8); break;
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case 0b01: target = static_cast<u64>(_dst->_u16); break;
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case 0b10: target = static_cast<u64>(_dst->_u32); break;
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case 0b11: target = _dst->_u64; break;
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}
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RI = target - 1;
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}
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(this->*_post)();
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}
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// ── 0x03A — JNE: Jumps if EQ flag is cleared ──
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void CPU::JNE() {
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fetchOperDst();
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if (!(RF & CPU::FLAG_EQUAL)) {
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u64 target;
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switch(_size) {
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case 0b00: target = static_cast<u64>(_dst->_u8); break;
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case 0b01: target = static_cast<u64>(_dst->_u16); break;
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case 0b10: target = static_cast<u64>(_dst->_u32); break;
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case 0b11: target = _dst->_u64; break;
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}
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RI = target - 1;
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}
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(this->*_post)();
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}
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// ── 0x03B — JIF: Jumps if Src is booleanly true ──
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void CPU::JIF() {
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fetchOperSrc();
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fetchOperDst();
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if (_src->_u64 != 0) {
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u64 target;
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switch(_size) {
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case 0b00: target = static_cast<u64>(_dst->_u8); break;
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case 0b01: target = static_cast<u64>(_dst->_u16); break;
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case 0b10: target = static_cast<u64>(_dst->_u32); break;
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case 0b11: target = _dst->_u64; break;
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}
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RI = target - 1;
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}
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(this->*_post)();
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}
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// ── 0x03C — JMR: Dst + Instruction Register -> Instruction Register ──
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void CPU::JMR() {
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fetchOperDst();
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i64 offset;
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switch (_size) {
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case 0b00: offset = static_cast<i64>(_dst->_i8); break; // 1 byte
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case 0b01: offset = static_cast<i64>(_dst->_i16); break; // 2 bytes
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case 0b10: offset = static_cast<i64>(_dst->_i32); break; // 4 bytes
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case 0b11: offset = _dst->_i64; break; // 8 bytes
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}
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RI = static_cast<u64>(static_cast<i64>(RI) + offset);
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}
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// ── 0x03D — JER: Dst + Instruction Register -> Instruction Register IF Flags.EQ ──
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void CPU::JER() {
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fetchOperDst();
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if (RF & CPU::FLAG_EQUAL) {
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i64 offset;
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switch (_size) {
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case 0b00: offset = static_cast<i64>(_dst->_i8); break;
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case 0b01: offset = static_cast<i64>(_dst->_i16); break;
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case 0b10: offset = static_cast<i64>(_dst->_i32); break;
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case 0b11: offset = _dst->_i64; break;
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}
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RI = static_cast<u64>(static_cast<i64>(RI) + offset);
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}
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}
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// ── 0x03E — JNR: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ ──
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void CPU::JNR() {
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fetchOperDst();
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if (!(RF & CPU::FLAG_EQUAL)) {
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i64 offset;
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switch (_size) {
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case 0b00: offset = static_cast<i64>(_dst->_i8); break;
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case 0b01: offset = static_cast<i64>(_dst->_i16); break;
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case 0b10: offset = static_cast<i64>(_dst->_i32); break;
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case 0b11: offset = _dst->_i64; break;
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}
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RI = static_cast<u64>(static_cast<i64>(RI) + offset);
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}
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}
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// ── 0x03F — JIR: Dst + Instruction Register -> Instruction Register IF Src ──
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void CPU::JIR() {
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fetchOperSrc();
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fetchOperDst();
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if (_src->_u64 != 0) {
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i64 offset;
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switch (_size) {
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case 0b00: offset = static_cast<i64>(_dst->_i8); break;
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case 0b01: offset = static_cast<i64>(_dst->_i16); break;
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case 0b10: offset = static_cast<i64>(_dst->_i32); break;
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case 0b11: offset = _dst->_i64; break;
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}
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RI = static_cast<u64>(static_cast<i64>(RI) + offset);
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}
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}
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}
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