185 lines
4.0 KiB
C++
185 lines
4.0 KiB
C++
#include "CPU.hpp"
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#include <spider/runtime/native/machine.hpp>
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#include <spider/runtime/memory/RAM.hpp>
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#include <spider/runtime/memory/Types.hpp>
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#include <spider/runtime/reel/InstrReel.hpp>
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#if __cplusplus >= 202002L
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#include <bit>
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#endif
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namespace spider {
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CPU::CPU()
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: RA{}, RB{}, RC{}, RD{},
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RX{}, RY{}, R0{}, R1{},
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R2{}, R3{}, R4{}, R5{},
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R6{}, R7{}, R8{}, R9{},
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RF{}, RI{}, RS{}, RZ{},
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RE{}, RN{}, RV{}, RM{},
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ALU0{}, ALU1{},
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_dst(nullptr), _src(nullptr),
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_opcode(0), _addrm(0), _size(0),
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_store(0), _post(&CPU::imp),
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_ram(nullptr), _reel(nullptr) {
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}
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CPU::~CPU() {}
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// Setup & Configuration //
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void CPU::hookRAM(RAM* ram) {
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this->_ram = ram;
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}
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void CPU::hookInstrReel(InstrReel* reel) {
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this->_reel = reel;
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}
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constexpr u64 CPU::getFlag(u64 mask) {
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if (!mask) return 0;
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#if __cplusplus >= 202002L
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return (RF & mask) >> std::countr_zero(mask);
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#elif defined(SPIDER_COMPILER_GCC_LIKE)
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return (RF & mask) >> __builtin_ctzll(mask);
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#elif defined(SPIDER_COMPILER_MSVC)
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return (RF & mask) >> _BitScanForward64(mask);
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#else
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// If you have reached this part,
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// please come up with a better alternative.
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u64 bits = RF & mask;
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while (mask && (mask >>= 1)) bits >>= 1;
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return bits;
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#endif
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}
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// Interaction with Reel //
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CPU::Fn CPU::addrModes[] = {
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&CPU::imm, &CPU::abs,
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&CPU::reg, &CPU::ind,
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&CPU::ptr, &CPU::idx,
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&CPU::sca, &CPU::dis
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};
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void CPU::fetchInstr() {
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u16 i = _reel->readU16(RI);
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const u16 oc = (i >> 7);
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_opcode = oc & 0x1FF; // GCC WHY!
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_addrm = static_cast<u8>((i >> 2) & 0x1F);
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_size = static_cast<u8>(i & 0x3);
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RI += 2;
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}
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void CPU::fetchOperDst() {
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// Move the operand ptrs
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_alu = &ALU0;
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_opers[1] = _opers[0];
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// call specific addressing mode
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(this->*(CPU::addrModes[_addrm]))();
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}
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void CPU::fetchOperSrc() {
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// set ALU
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_alu = &ALU1;
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// call specific addressing mode
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(this->*(CPU::addrModes[_addrm]))();
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// modify the _addrm register
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_addrm = static_cast<u8>((_addrm >> 3) & 0x1F);
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_addrm++;
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}
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void CPU::execute() {
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(this->*(CPU::addrModes[_opcode]))();
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}
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// Addressing Modes //
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/**
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* Implied Addressing Mode
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*/
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void CPU::imp() {
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// Nothing //
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}
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/**
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* Immediate Addressing Mode
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*/
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void CPU::imm() {
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_reel->loadRegister(RI, _size, _alu);
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_opers[0] = _alu;
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_post = &CPU::imp;
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RI += 1 << _size;
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}
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/**
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* Absolute Addressing Mode
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*/
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void CPU::abs() {
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// Load the actual ptr into the ALU
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u8 mm = u8(getFlag(CPU::FLAG_MEMORY_MODE));
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_reel->loadRegister(RI, mm, _alu);
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RI += 1 << mm;
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// read the memory from RAM
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_store = _alu->_u64;
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_ram->loadRegister(_store, _size, _alu);
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_post = &CPU::psw;
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}
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/**
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* Register Addressing Mode
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*/
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void CPU::reg() { // NOT FINISHED
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// Two consecutive registers can be declared
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// Shift if the top part will become .reg too
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u8 sh = ((_addrm & 0b11000) == 0b11000) * 4;
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u8 use = 1 - (sh >> 2); // (sh / 4)
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// get byte
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u8 reg = (_reel->readU8(RI) >> sh) & 0xF;
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_alu = &GPR[reg];
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RI += use;
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// store no-op
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_post = &CPU::imp;
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}
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/**
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* Indrect Addressing Mode
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*/
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void CPU::ind() {}
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/**
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* Pointer Addressing Mode
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*/
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void CPU::ptr() {}
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/**
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* Indexed Addressing Mode
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*/
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void CPU::idx() {}
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/**
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* Scaled Addressing Mode
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*/
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void CPU::sca() {}
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/**
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* Displaced Addressing Mode
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*/
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void CPU::dis() {}
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/**
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* Post Write Action
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*/
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void CPU::psw() {}
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}
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