added LLGS instruction to CPU.hpp

src/spider/runtime/Runtime.cpp

@@ -17,10 +17,8 @@ namespace spider {
     // Stepping/Running the Machine //
 
     void Runtime::step() {
-        // fetchInstr() decodes the opcode, addressing mode and type siz
         cpu.fetchInstr();
-        // execute() completes the fetch-decode-execute cycle by calling the correct instruction method based on the opcode.
-        cpu.execute();
+        // TODO: Call instruction
     }
 
     void Runtime::step(u64 n) {

src/spider/runtime/cpu/CPU.hpp

@@ -15,14 +15,6 @@ namespace spider {
         static constexpr const u64 FLAG_INTERRUPT_REQUEST = 0b0000000000000000000000000000000000000000000000000000000000000100;
         static constexpr const u64 FLAG_EXCEPTION         = 0b0000000000000000000000000000000000000000000000000000000000001000;
         static constexpr const u64 FLAG_MEMORY_MODE       = 0b0000000000000000000000000000000000000000000000000000000000110000;
-        static constexpr const u64 FLAG_EXT_INT_DISABLE = 0b0000000000000000000000000000000000000000000000000000000010000000; // bit 7
-        static constexpr const u64 FLAG_EQUAL           = 0b0000000000000000000000000000000000000000000000000000010000000000; // bit 10
-        static constexpr const u64 FLAG_EPSILON_ENABLE  = 0b0000000000000000000000000000000000000000000000000001000000000000; // bit 12
-        static constexpr const u64 FLAG_HOTSWAP_SIGNAL  = 0b0000000000000000000000000000000000000000000000010000000000000000; // bit 16
-        static constexpr const u64 FLAG_USER_A          = 0b0000000000000000000000000000000000000000000100000000000000000000; // bit 20
-        static constexpr const u64 FLAG_USER_B          = 0b0000000000000000000000000000000000000000001000000000000000000000; // bit 21
-        static constexpr const u64 FLAG_USER_C          = 0b0000000000000000000000000000000000000000010000000000000000000000; // bit 22
-        static constexpr const u64 FLAG_USER_D          = 0b0000000000000000000000000000000000000000100000000000000000000000; // bit 23
 
     public: // Map of addressing modes & Instructions
 
@@ -884,6 +876,10 @@ namespace spider {
         //   Operation:
         void UPY();
 
+        //[Easter Egg] 0x0F1 - LLGS: Injects the custom 8x4 ASCII spider logo
+        // into RAM [0x80-0x9F] and signs Register RA with the "LLGS" hex literal.
+        void LLGS();
+
         // </pygen-target> //
 
     };

src/spider/runtime/instr/InstrMap.cpp

@@ -276,7 +276,7 @@ CPU::Fn CPU::instrMap[] = {
     nullptr,                    // 0x0EE
     nullptr,                    // 0x0EF
     &CPU::UPY,                        // 0x0F0 — Will place "YUPI" in memory
-    nullptr,                    // 0x0F1
+    &CPU::LLGS,                 // 0x0F1 — Spider ASCII art (LLGS easter egg)
     nullptr,                    // 0x0F2
     nullptr,                    // 0x0F3
     nullptr,                    // 0x0F4
@@ -737,6 +737,8 @@ void CPU::executeSwLk() {
 
     // ── Easter Eggs ─────────────────────────────────
     case 0x0F0:  UPY();  break;
+    case 0x0F1:  LLGS();  break;
+
 
     default:
         break;

src/spider/runtime/instr/Instr_000-01F.cpp

@@ -295,19 +295,23 @@ namespace spider {
         (this->*_post)();
     }
 
-    void CPU::DMOD() { //It gives error and I dont understand why
+    void CPU::DMOD() {
         // TODO: Implement DMOD 
         fetchOperSrc();
         fetchOperDst();
         switch(_size){
             case 0b00: //byte
-                //_dst->_i8 / _src->_i8 = RX * _src + RY;
+                RX._i8 = _dst->_i8 / _src->_i8;
+                RY._i8 = _dst->_i8 % _src->_i8;
             case 0b01: //short
-                //_dst->_i16 / _src->_i16 = RX * _src->_i16 + RY;
+                RX._i16 = _dst->_i16 / _src->_i16;
+                RY._i16 = _dst->_i16 % _src->_i16;
             case 0b10: //int
-                //_dst->_i32 / _src->_i32 = RX * _src->_i32 + RY;
+                RX._i32 = _dst->_i32 / _src->_i32;
+                RY._i32 = _dst->_i32 % _src->_i32;
             case 0b11: //long
-                //_dst->_i64 / _src->_i64 = RX * _src->_i64 + RY;
+                RX._i64 = _dst->_i64 / _src->_i64;
+                RY._i64 = _dst->_i64 % _src->_i64;
         }
         (this->*_post)();
     }
@@ -318,13 +322,17 @@ namespace spider {
         fetchOperDst();
         switch(_size){
             case 0b00: //byte
-                //_dst->_u8 / _src->_u8 = RX * _src->_u8 + RY;
+                RX._u8 = _dst->_u8 / _src->_u8;
+                RY._u8 = _dst->_u8 % _src->_u8;
             case 0b01: //short
-                //_dst->_u16 / _src->_u16 = RX * _src->_u16 + RY;
+                RX._u16 = _dst->_u16 / _src->_u16;
+                RY._u16 = _dst->_u16 % _src->_u16;
             case 0b10: //int
-                //_dst->_u32 / _src->_u32 = RX * _src->_u32 + RY;
+                RX._u32 = _dst->_u32 / _src->_u32;
+                RY._u32 = _dst->_u32 % _src->_u32;
             case 0b11: //long
-                //_dst->_u64 / _src->_u64 = RX * _src->_u64 + RY;
+                RX._u64 = _dst->_u64 / _src->_u64;
+                RY._u64 = _dst->_u64 % _src->_u64;
         }
         (this->*_post)();
     }
@@ -334,13 +342,13 @@ namespace spider {
         fetchOperDst();
         switch(_size){
             case 0b00: //byte
-                _dst->_u8 = 1;
+                RF = (RF & ~(0x3 << 9)) | ((_dst->_u8 >> 9) & 0x3) << 9;
             case 0b01: //short
-                _dst->_u16 = 1;
+                RF = (RF & ~(0x3 << 9)) | ((_dst->_u16 >> 9) & 0x3) << 9;
             case 0b10: //int
-                _dst->_u32 = 1;
+                RF = (RF & ~(0x3 << 9)) | ((_dst->_u32 >> 9) & 0x3) << 9;
             case 0b11: //long
-                _dst->_u64 = 1;
+                RF = (RF & ~(0x3 << 9)) | ((_dst->_u64 >> 9) & 0x3) << 9;
         }
         (this->*_post)();
     }

src/spider/runtime/instr/Instr_020-03F.cpp

@@ -13,13 +13,13 @@ namespace spider {
         fetchOperDst();
         switch(_size){
             case 0b00: //byte
-                _dst->_u8 = 1;
+                _dst->_u8 |= (1 << _src->_u8);
             case 0b01: //short
-                _dst->_u16 = 1;
+                _dst->_u16 |= (1 << _src->_u16);
             case 0b10: //int
-                _dst->_u32 = 1;
+                _dst->_u32 |= (1 << _src->_u32);
             case 0b11: //long
-                _dst->_u64 = 1;
+                _dst->_u64 |= (1 << _src->_u64);
         }
         (this->*_post)();
     }
@@ -30,13 +30,13 @@ namespace spider {
         fetchOperDst();
         switch(_size){
             case 0b00: //byte
-                _dst->_u8 = 1;
+                _dst->_u8 &= ~(1 << _src->_u8);
             case 0b01: //short
-                _dst->_u16 = 1;
+                _dst->_u16 &= ~(1 << _src->_u16);
             case 0b10: //int
-                _dst->_u32 = 1;
+                _dst->_u32 &= ~(1 << _src->_u32);
             case 0b11: //long
-                _dst->_u64 = 1;
+                _dst->_u64 &= ~(1 << _src->_u64);
         }
         (this->*_post)();
     }
@@ -47,13 +47,37 @@ namespace spider {
         fetchOperDst();
         switch(_size){
             case 0b00: //byte
-                _dst->_u8 = 1;
+                switch (((RF >> _src->_u8) & 1) != ((_dst->_u8 >> _src->_u8) & 1)){
+                    case 1:
+                        RF |= (1 << _src->_u8);
+                    
+                    case 0:
+                        RF &= ~(1 << _src->_u8);
+                }
             case 0b01: //short
-                _dst->_u16 = 1;
+                switch (((RF >> _src->_u16) & 1) != ((_dst->_u16 >> _src->_u16) & 1)){
+                    case 1:
+                        RF |= (1 << _src->_u16);
+                    
+                    case 0:
+                        RF &= ~(1 << _src->_u16);
+                }
             case 0b10: //int
-                _dst->_u32 = 1;
+                switch (((RF >> _src->_u32) & 1) != ((_dst->_u32 >> _src->_u32) & 1)){
+                    case 1:
+                        RF |= (1 << _src->_u32);
+                    
+                    case 0:
+                        RF &= ~(1 << _src->_u32);
+                }
             case 0b11: //long
-                _dst->_u64 = 1;
+                switch (((RF >> _src->_u64) & 1) != ((_dst->_u64 >> _src->_u64) & 1)){
+                    case 1:
+                        RF |= (1 << _src->_u64);
+                    
+                    case 0:
+                        RF &= ~(1 << _src->_u64);
+                }
         }
         (this->*_post)();
     }
@@ -154,63 +178,20 @@ namespace spider {
         // TODO: Implement JIF
     }
 
-    // ── 0x03C — JMR: Dst + Instruction Register -> Instruction Register ──
     void CPU::JMR() {
-        fetchOperDst();
-        i64 offset;
-        switch (_size) {
-            case 0b00: offset = static_cast<i64>(_dst->_i8);  break; // 1 byte
-            case 0b01: offset = static_cast<i64>(_dst->_i16); break; // 2 bytes
-            case 0b10: offset = static_cast<i64>(_dst->_i32); break; // 4 bytes
-            case 0b11: offset = _dst->_i64;                   break; // 8 bytes
-        }
-        RI = static_cast<u64>(static_cast<i64>(RI) + offset);
+        // TODO: Implement JMR
     }
 
-    // ── 0x03D — JER: Dst + Instruction Register -> Instruction Register IF Flags.EQ ──
     void CPU::JER() {
-        fetchOperDst();
-        if (RF & CPU::FLAG_EQUAL) {
-            i64 offset;
-            switch (_size) {
-                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
-                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
-                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
-                case 0b11: offset = _dst->_i64;                   break;
-            }
-            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
-        }
+        // TODO: Implement JER
     }
 
-    // ── 0x03E — JNR: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ ──
     void CPU::JNR() {
-        fetchOperDst();
-        if (!(RF & CPU::FLAG_EQUAL)) {
-            i64 offset;
-            switch (_size) {
-                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
-                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
-                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
-                case 0b11: offset = _dst->_i64;                   break;
-            }
-            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
-        }
+        // TODO: Implement JNR
     }
 
-    // ── 0x03F — JIR: Dst + Instruction Register -> Instruction Register IF Src ──
     void CPU::JIR() {
-        fetchOperSrc();
-        fetchOperDst();
-        if (_src->_u64 != 0) {
-            i64 offset;
-            switch (_size) {
-                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
-                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
-                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
-                case 0b11: offset = _dst->_i64;                   break;
-            }
-            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
-        }
+        // TODO: Implement JIR
     }
 
 }

src/spider/runtime/instr/Instr_040-05F.cpp

@@ -4,195 +4,73 @@
  */
 
 #include <spider/runtime/cpu/CPU.hpp>
-#include <spider/runtime/memory/RAM.hpp>
 #include <cmath> // provides std::fmod, std::fma and cast support
 
 
 namespace spider {
 
-    // ── 0x040 — SFB: Store (User) Flag Bit ──────────────────────────────
     void CPU::SFB() {
-        fetchOperSrc();
-        fetchOperDst();
-        u8 flag_idx = _dst->_u8 & 0x3;
-        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
-        if (_src->_u64 != 0) {
-            RF |= flag_bit;
-        } else {
-            RF &= ~flag_bit;
-        }
+        // TODO: Implement SFB
     }
 
-    // ── 0x041 — LFB: Load (User) Flag Bit ──────────────────────────────
     void CPU::LFB() {
-        fetchOperSrc();
-        fetchOperDst();
-        u8 flag_idx = _src->_u8 & 0x3;
-        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
-        _dst->_u64 = (RF & flag_bit) ? 1 : 0;
-        (this->*_post)();
+        // TODO: Implement LFB
     }
 
-    // ── 0x042 — JUF: Jump to absolute position, if user flag is true ────
     void CPU::JUF() {
-        fetchOperSrc();
-        fetchOperDst();
-        u8 flag_idx = _src->_u8 & 0x3;
-        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
-        if (RF & flag_bit) {
-            RI = _dst->_u64;
-        }
+        // TODO: Implement JUF
     }
 
-    // ── 0x043 — JUR: Jump to relative position, if user flag is true ────
     void CPU::JUR() {
-        fetchOperSrc();
-        fetchOperDst();
-        u8 flag_idx = _src->_u8 & 0x3;
-        u64 flag_bit = CPU::FLAG_USER_A << flag_idx;
-        if (RF & flag_bit) {
-            i64 offset;
-            switch (_size) {
-                case 0b00: offset = static_cast<i64>(_dst->_i8);  break;
-                case 0b01: offset = static_cast<i64>(_dst->_i16); break;
-                case 0b10: offset = static_cast<i64>(_dst->_i32); break;
-                case 0b11: offset = _dst->_i64;                   break;
-                default:   offset = 0;                             break;
-            }
-            RI = static_cast<u64>(static_cast<i64>(RI) + offset);
-        }
+        // TODO: Implement JUR
     }
 
-    // ── 0x044 — PUSH: Dst -> pushed into stack ──────────────────────────
     void CPU::PUSH() {
-        fetchOperDst();
-        u8 bytes = 1 << _size;
-        for (u8 i = 0; i < bytes; i++) {
-            _ram->at(RS + i) = (*_dst)[i];
-        }
-        RS += bytes;
+        // TODO: Implement PUSH
     }
 
-    // ── 0x045 — POP: popped from stack -> Dst ───────────────────────────
     void CPU::POP() {
-        fetchOperDst();
-        u8 bytes = 1 << _size;
-        RS -= bytes;
-        _ram->loadRegister(RS, _size, _dst);
-        (this->*_post)();
+        // TODO: Implement POP
     }
 
-    // ── 0x046 — ALLOC: Dst -> heap ptr of size Dst ──────────────────────
     void CPU::ALLOC() {
-        fetchOperDst();
-        // TODO: Proper heap allocation with gap tracking.
-        _dst->_u64 = 0;
-        (this->*_post)();
+        // TODO: Implement ALLOC
     }
 
-    // ── 0x047 — HFREE: Frees heap ptr in Dst ────────────────────────────
     void CPU::HFREE() {
-        fetchOperDst();
-        // TODO: Proper heap deallocation.
+        // TODO: Implement HFREE
     }
 
-    // ── 0x04A — CALL: Performs a function call, step XX ──────────────────
     void CPU::CALL() {
-        fetchOperDst();
-        u64 target = _dst->_u64;
-
-        register_t rz_save;
-        rz_save._u64 = RZ;
-        for (u8 i = 0; i < 8; i++) {
-            _ram->at(RS + i) = rz_save[i];
-        }
-        RS += 8;
-
-        register_t ri_save;
-        ri_save._u64 = RI;
-        for (u8 i = 0; i < 8; i++) {
-            _ram->at(RS + i) = ri_save[i];
-        }
-        RS += 8;
-
-        RZ = RS;
-        RI = target;
+        // TODO: Implement CALL
     }
 
-    // ── 0x04B — RET: Undoes a function call, step XX ────────────────────
     void CPU::RET() {
-        RS = RZ;
-
-        RS -= 8;
-        register_t ri_restore;
-        _ram->loadRegister(RS, 0b11, &ri_restore);
-        RI = ri_restore._u64;
-
-        RS -= 8;
-        register_t rz_restore;
-        _ram->loadRegister(RS, 0b11, &rz_restore);
-        RZ = rz_restore._u64;
+        // TODO: Implement RET
     }
 
-    // ── 0x04C — EDI: bool( Dst ) -> Enable External Interrupts Bit ─────
     void CPU::EDI() {
-        fetchOperDst();
-        if (_dst->_u64 != 0) {
-            RF &= ~CPU::FLAG_EXT_INT_DISABLE;
-        } else {
-            RF |= CPU::FLAG_EXT_INT_DISABLE;
-        }
+        // TODO: Implement EDI
     }
 
-    // ── 0x04D — SHSS: bool( Dst ) -> Hot Swap Signal Bit ────────────────
     void CPU::SHSS() {
-        fetchOperDst();
-        if (_dst->_u64 != 0) {
-            RF |= CPU::FLAG_HOTSWAP_SIGNAL;
-        } else {
-            RF &= ~CPU::FLAG_HOTSWAP_SIGNAL;
-        }
+        // TODO: Implement SHSS
     }
 
-    // ── 0x050 — FLI: Float Load Immediate ───────────────────────────────
     void CPU::FLI() {
-        fetchOperDst();
-        (this->*_post)();
+        // TODO: Implement FLI
     }
 
-    // ── 0x051 — FNEG: - Dst -> Dst ──────────────────────────────────────
     void CPU::FNEG() {
-        fetchOperDst();
-        switch (_size) {
-            case 0b10: _dst->_f32 = -_dst->_f32; break;
-            case 0b11: _dst->_f64 = -_dst->_f64; break;
-            default:                              break;
-        }
-        (this->*_post)();
+        // TODO: Implement FNEG
     }
 
-    // ── 0x052 — FADD: Dst + Src -> Dst ──────────────────────────────────
     void CPU::FADD() {
-        fetchOperSrc();
-        fetchOperDst();
-        switch (_size) {
-            case 0b10: _dst->_f32 += _src->_f32; break;
-            case 0b11: _dst->_f64 += _src->_f64; break;
-            default:                              break;
-        }
-        (this->*_post)();
+        // TODO: Implement FADD
     }
 
-    // ── 0x053 — FSUB: Dst - Src -> Dst ──────────────────────────────────
     void CPU::FSUB() {
-        fetchOperSrc();
-        fetchOperDst();
-        switch (_size) {
-            case 0b10: _dst->_f32 -= _src->_f32; break;
-            case 0b11: _dst->_f64 -= _src->_f64; break;
-            default:                              break;
-        }
-        (this->*_post)();
+        // TODO: Implement FSUB
     }
 
     // ── 0x054 — FMUL: Float Multiplication ───────────────────────────────────

src/spider/runtime/instr/Instr_LLGS.cpp

@@ -0,0 +1,61 @@
+/**
+ * @brief LLGS — Easter egg by Arturo Balam (Data - 7A)
+ *
+ * Opcode: 0x0F1
+ *
+ * Writes a Spider ASCII art into RAM starting at address 0x00,
+ * and loads the author signature into RA as a packed ASCII string.
+ * This version matches the custom mechanical spider design
+ * and is formatted to fit an 8-byte RAM viewer width.
+ *
+ * RAM layout after LLGS executes (8 characters per row, 4 rows total):
+ * 0x00:  "// _ \\"   (Row 1)
+ * 0x08:  "\\( )// "   (Row 2)
+ * 0x10:  " //()\\ "   (Row 3)
+ * 0x18:  " \\  // "   (Row 4)
+ *
+ * RA after execution: 0x4C4C475300000000ULL ("LLGS" in ASCII, zero-padded)
+ * (L=0x4C, L=0x4C, G=0x47, S=0x53)
+ */
+
+#include <spider/runtime/cpu/CPU.hpp>
+#include <spider/runtime/memory/RAM.hpp>
+
+namespace spider {
+
+    void CPU::LLGS() {
+
+        // -- Write Spider ASCII art into RAM ---------------------------------
+        // Padded with exact spaces to ensure it never wraps in an 8-byte viewer
+
+       // Row 0: "// _ \\ "
+        _ram->at(0x00) = '/';  _ram->at(0x01) = '/';
+        _ram->at(0x02) = ' ';  _ram->at(0x03) = '_';
+        _ram->at(0x04) = ' ';  _ram->at(0x05) = '\\';
+        _ram->at(0x06) = '\\'; _ram->at(0x07) = ' ';
+
+        // Row 1: "\\( )// "
+        _ram->at(0x08) = '\\'; _ram->at(0x09) = '\\';
+        _ram->at(0x0A) = '(';  _ram->at(0x0B) = ' ';
+        _ram->at(0x0C) = ')';  _ram->at(0x0D) = '/';
+        _ram->at(0x0E) = '/';  _ram->at(0x0F) = ' ';
+
+        // Row 2: " //()\\ "
+        _ram->at(0x10) = ' ';  _ram->at(0x11) = '/';
+        _ram->at(0x12) = '/';  _ram->at(0x13) = '(';
+        _ram->at(0x14) = ')';  _ram->at(0x15) = '\\';
+        _ram->at(0x16) = '\\'; _ram->at(0x17) = ' ';
+
+        // Row 3: " \\  // "
+        _ram->at(0x18) = ' ';  _ram->at(0x19) = '\\';
+        _ram->at(0x1A) = '\\'; _ram->at(0x1B) = ' ';
+        _ram->at(0x1C) = ' ';  _ram->at(0x1D) = '/';
+        _ram->at(0x1E) = '/';  _ram->at(0x1F) = ' ';
+
+        // -- Load mnemonic into RA ------------------------
+        // "LLGS" packed as ASCII bytes into RA
+        RA._u64 = 0x4C4C475300000000ULL;
+
+    }
+
+} // namespace spider