added LLGS instruction to CPU.hpp
This commit is contained in:
@@ -83,11 +83,11 @@ namespace spider {
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/**
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/**
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* Pointer to the current RAM hooked into
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* Pointer to the current RAM hooked into
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* the CPU.
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* the CPU.
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*
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*
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* It is unproved whether having the RAM directly
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* It is unproved whether having the RAM directly
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* into the CPU is better than not, or whether a
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* into the CPU is better than not, or whether a
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* virtual BUS is better.
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* virtual BUS is better.
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*
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*
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* Alas, this way we can have a CPU state switch
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* Alas, this way we can have a CPU state switch
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* between memory and instruction banks.
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* between memory and instruction banks.
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*/
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*/
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@@ -96,7 +96,7 @@ namespace spider {
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/**
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/**
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* Pointer to the current Instruction Reel
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* Pointer to the current Instruction Reel
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* hooked into the CPU.
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* hooked into the CPU.
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*
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*
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* Ditto as RAM.
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* Ditto as RAM.
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*/
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*/
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InstrReel* _reel;
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InstrReel* _reel;
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@@ -112,7 +112,7 @@ namespace spider {
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~CPU();
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~CPU();
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public:
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public:
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CPU& operator=(const CPU& other) = default;
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CPU& operator=(const CPU& other) = default;
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CPU& operator=(CPU&& other) noexcept = default;
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CPU& operator=(CPU&& other) noexcept = default;
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@@ -124,7 +124,7 @@ namespace spider {
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void hookInstrReel(InstrReel* reel);
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void hookInstrReel(InstrReel* reel);
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constexpr u64 getFlag(u64 mask);
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constexpr u64 getFlag(u64 mask);
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public:
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public:
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/**
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/**
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@@ -137,11 +137,11 @@ namespace spider {
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* Fetches the destination operand,
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* Fetches the destination operand,
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* by calling the appropriate addressing
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* by calling the appropriate addressing
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* mode.
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* mode.
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*
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*
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* Will read the bottom 3 bits.
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* Will read the bottom 3 bits.
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* For instructions with two operands,
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* For instructions with two operands,
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* call Src first.
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* call Src first.
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*
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*
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* The internal variable _addrm
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* The internal variable _addrm
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* will not be modified. It will
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* will not be modified. It will
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* be important when writing
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* be important when writing
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@@ -151,14 +151,14 @@ namespace spider {
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/**
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/**
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* Fetches the source operand.
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* Fetches the source operand.
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*
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*
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* For use in two operand instructions.
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* For use in two operand instructions.
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*
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*
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* Will read the bottom 3 bits. It will
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* Will read the bottom 3 bits. It will
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* then shift the _addrm 3 spaces
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* then shift the _addrm 3 spaces
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* to ensure it aligns with the DST
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* to ensure it aligns with the DST
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* next.
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* next.
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*
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*
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* Additionally, it will add 1 to _addrm
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* Additionally, it will add 1 to _addrm
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* to account with
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* to account with
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*/
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*/
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@@ -176,7 +176,7 @@ namespace spider {
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* a large switch statement. Only suitable
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* a large switch statement. Only suitable
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* for environments where the instruction
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* for environments where the instruction
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* map is not possible.
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* map is not possible.
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*
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*
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* This has yet to be proved!!!
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* This has yet to be proved!!!
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*/
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*/
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void executeSwLk();
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void executeSwLk();
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@@ -197,32 +197,32 @@ namespace spider {
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* Absolute Addressing Mode
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* Absolute Addressing Mode
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*/
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*/
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void abs();
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void abs();
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/**
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/**
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* Register Addressing Mode
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* Register Addressing Mode
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*/
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*/
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void reg();
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void reg();
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/**
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/**
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* Indrect Addressing Mode
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* Indrect Addressing Mode
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*/
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*/
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void ind();
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void ind();
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/**
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/**
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* Pointer Addressing Mode
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* Pointer Addressing Mode
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*/
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*/
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void ptr();
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void ptr();
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/**
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/**
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* Indexed Addressing Mode
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* Indexed Addressing Mode
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*/
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*/
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void idx();
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void idx();
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/**
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/**
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* Scaled Addressing Mode
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* Scaled Addressing Mode
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*/
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*/
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void sca();
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void sca();
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/**
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/**
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* Displaced Addressing Mode
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* Displaced Addressing Mode
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*/
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*/
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@@ -533,22 +533,22 @@ namespace spider {
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// [System] 0x040 — SFB: Store (User) Flag Bit
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// [System] 0x040 — SFB: Store (User) Flag Bit
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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// Operation:
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void SFB();
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void SFB();
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// [System] 0x041 — LFB: Load (User) Flag Bit
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// [System] 0x041 — LFB: Load (User) Flag Bit
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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// Operation:
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void LFB();
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void LFB();
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// [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true
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// [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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// Operation:
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void JUF();
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void JUF();
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// [Branch] 0x043 — JUR: Jump to relative position, if user flag is true
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// [Branch] 0x043 — JUR: Jump to relative position, if user flag is true
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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// Operation:
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void JUR();
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void JUR();
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// [Memory] 0x044 — PUSH: Push to stack
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// [Memory] 0x044 — PUSH: Push to stack
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@@ -593,7 +593,7 @@ namespace spider {
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// [Floating Point] 0x050 — FLI: Float Load Immediate
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// [Floating Point] 0x050 — FLI: Float Load Immediate
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
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// Operation:
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// Operation:
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void FLI();
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void FLI();
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// [Floating Point] 0x051 — FNEG: Float negate
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// [Floating Point] 0x051 — FNEG: Float negate
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@@ -808,74 +808,78 @@ namespace spider {
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// [Matrix] 0x080 — MADD: Matrix Addition
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// [Matrix] 0x080 — MADD: Matrix Addition
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void MADD();
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void MADD();
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// [Matrix] 0x081 — MSUB: Matrix Subtraction
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// [Matrix] 0x081 — MSUB: Matrix Subtraction
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void MSUB();
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void MSUB();
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// [Matrix] 0x082 — MMUL: Matrix Multiply
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// [Matrix] 0x082 — MMUL: Matrix Multiply
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void MMUL();
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void MMUL();
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// [Matrix] 0x083 — MINV: Matrix Inverse
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// [Matrix] 0x083 — MINV: Matrix Inverse
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void MINV();
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void MINV();
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// [Matrix] 0x084 — MTRA: Matrix Transpose
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// [Matrix] 0x084 — MTRA: Matrix Transpose
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void MTRA();
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void MTRA();
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// [Matrix] 0x085 — MDET: Matrix Determinant
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// [Matrix] 0x085 — MDET: Matrix Determinant
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void MDET();
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void MDET();
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// [Quaternion] 0x086 — QMKA: Quaternion Make from Angles
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// [Quaternion] 0x086 — QMKA: Quaternion Make from Angles
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void QMKA();
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void QMKA();
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// [Quaternion] 0x087 — QMUL: Quaternion Multiply
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// [Quaternion] 0x087 — QMUL: Quaternion Multiply
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void QMUL();
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void QMUL();
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// [SIMD] 0x08A — XADD: SIMD Addition
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// [SIMD] 0x08A — XADD: SIMD Addition
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void XADD();
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void XADD();
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// [SIMD] 0x08B — XSUB: SIMD Subtract
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// [SIMD] 0x08B — XSUB: SIMD Subtract
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void XSUB();
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void XSUB();
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// [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add
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// [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void XAMA();
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void XAMA();
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// [SIMD] 0x08D — XMUL: SIMD Multiply
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// [SIMD] 0x08D — XMUL: SIMD Multiply
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void XMUL();
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void XMUL();
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// [SIMD] 0x08E — XDIV: SIMD Divide
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// [SIMD] 0x08E — XDIV: SIMD Divide
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void XDIV();
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void XDIV();
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// [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory
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// [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Operation:
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// Operation:
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void UPY();
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void UPY();
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//[Easter Egg] 0x0F1 - LLGS: Injects the custom 8x4 ASCII spider logo
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// into RAM [0x80-0x9F] and signs Register RA with the "LLGS" hex literal.
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void LLGS();
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// </pygen-target> //
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// </pygen-target> //
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};
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};
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