added LLGS instruction to CPU.hpp

This commit is contained in:
Arturo
2026-04-11 11:50:37 -06:00
parent c3c94583f4
commit cdf14cf545

View File

@@ -83,11 +83,11 @@ namespace spider {
/** /**
* Pointer to the current RAM hooked into * Pointer to the current RAM hooked into
* the CPU. * the CPU.
* *
* It is unproved whether having the RAM directly * It is unproved whether having the RAM directly
* into the CPU is better than not, or whether a * into the CPU is better than not, or whether a
* virtual BUS is better. * virtual BUS is better.
* *
* Alas, this way we can have a CPU state switch * Alas, this way we can have a CPU state switch
* between memory and instruction banks. * between memory and instruction banks.
*/ */
@@ -96,7 +96,7 @@ namespace spider {
/** /**
* Pointer to the current Instruction Reel * Pointer to the current Instruction Reel
* hooked into the CPU. * hooked into the CPU.
* *
* Ditto as RAM. * Ditto as RAM.
*/ */
InstrReel* _reel; InstrReel* _reel;
@@ -112,7 +112,7 @@ namespace spider {
~CPU(); ~CPU();
public: public:
CPU& operator=(const CPU& other) = default; CPU& operator=(const CPU& other) = default;
CPU& operator=(CPU&& other) noexcept = default; CPU& operator=(CPU&& other) noexcept = default;
@@ -124,7 +124,7 @@ namespace spider {
void hookInstrReel(InstrReel* reel); void hookInstrReel(InstrReel* reel);
constexpr u64 getFlag(u64 mask); constexpr u64 getFlag(u64 mask);
public: public:
/** /**
@@ -137,11 +137,11 @@ namespace spider {
* Fetches the destination operand, * Fetches the destination operand,
* by calling the appropriate addressing * by calling the appropriate addressing
* mode. * mode.
* *
* Will read the bottom 3 bits. * Will read the bottom 3 bits.
* For instructions with two operands, * For instructions with two operands,
* call Src first. * call Src first.
* *
* The internal variable _addrm * The internal variable _addrm
* will not be modified. It will * will not be modified. It will
* be important when writing * be important when writing
@@ -151,14 +151,14 @@ namespace spider {
/** /**
* Fetches the source operand. * Fetches the source operand.
* *
* For use in two operand instructions. * For use in two operand instructions.
* *
* Will read the bottom 3 bits. It will * Will read the bottom 3 bits. It will
* then shift the _addrm 3 spaces * then shift the _addrm 3 spaces
* to ensure it aligns with the DST * to ensure it aligns with the DST
* next. * next.
* *
* Additionally, it will add 1 to _addrm * Additionally, it will add 1 to _addrm
* to account with * to account with
*/ */
@@ -176,7 +176,7 @@ namespace spider {
* a large switch statement. Only suitable * a large switch statement. Only suitable
* for environments where the instruction * for environments where the instruction
* map is not possible. * map is not possible.
* *
* This has yet to be proved!!! * This has yet to be proved!!!
*/ */
void executeSwLk(); void executeSwLk();
@@ -197,32 +197,32 @@ namespace spider {
* Absolute Addressing Mode * Absolute Addressing Mode
*/ */
void abs(); void abs();
/** /**
* Register Addressing Mode * Register Addressing Mode
*/ */
void reg(); void reg();
/** /**
* Indrect Addressing Mode * Indrect Addressing Mode
*/ */
void ind(); void ind();
/** /**
* Pointer Addressing Mode * Pointer Addressing Mode
*/ */
void ptr(); void ptr();
/** /**
* Indexed Addressing Mode * Indexed Addressing Mode
*/ */
void idx(); void idx();
/** /**
* Scaled Addressing Mode * Scaled Addressing Mode
*/ */
void sca(); void sca();
/** /**
* Displaced Addressing Mode * Displaced Addressing Mode
*/ */
@@ -533,22 +533,22 @@ namespace spider {
// [System] 0x040 — SFB: Store (User) Flag Bit // [System] 0x040 — SFB: Store (User) Flag Bit
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F // Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
// Operation: // Operation:
void SFB(); void SFB();
// [System] 0x041 — LFB: Load (User) Flag Bit // [System] 0x041 — LFB: Load (User) Flag Bit
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F // Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
// Operation: // Operation:
void LFB(); void LFB();
// [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true // [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F // Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
// Operation: // Operation:
void JUF(); void JUF();
// [Branch] 0x043 — JUR: Jump to relative position, if user flag is true // [Branch] 0x043 — JUR: Jump to relative position, if user flag is true
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F // Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
// Operation: // Operation:
void JUR(); void JUR();
// [Memory] 0x044 — PUSH: Push to stack // [Memory] 0x044 — PUSH: Push to stack
@@ -593,7 +593,7 @@ namespace spider {
// [Floating Point] 0x050 — FLI: Float Load Immediate // [Floating Point] 0x050 — FLI: Float Load Immediate
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C // Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
// Operation: // Operation:
void FLI(); void FLI();
// [Floating Point] 0x051 — FNEG: Float negate // [Floating Point] 0x051 — FNEG: Float negate
@@ -808,74 +808,78 @@ namespace spider {
// [Matrix] 0x080 — MADD: Matrix Addition // [Matrix] 0x080 — MADD: Matrix Addition
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void MADD(); void MADD();
// [Matrix] 0x081 — MSUB: Matrix Subtraction // [Matrix] 0x081 — MSUB: Matrix Subtraction
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void MSUB(); void MSUB();
// [Matrix] 0x082 — MMUL: Matrix Multiply // [Matrix] 0x082 — MMUL: Matrix Multiply
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void MMUL(); void MMUL();
// [Matrix] 0x083 — MINV: Matrix Inverse // [Matrix] 0x083 — MINV: Matrix Inverse
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void MINV(); void MINV();
// [Matrix] 0x084 — MTRA: Matrix Transpose // [Matrix] 0x084 — MTRA: Matrix Transpose
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void MTRA(); void MTRA();
// [Matrix] 0x085 — MDET: Matrix Determinant // [Matrix] 0x085 — MDET: Matrix Determinant
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void MDET(); void MDET();
// [Quaternion] 0x086 — QMKA: Quaternion Make from Angles // [Quaternion] 0x086 — QMKA: Quaternion Make from Angles
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void QMKA(); void QMKA();
// [Quaternion] 0x087 — QMUL: Quaternion Multiply // [Quaternion] 0x087 — QMUL: Quaternion Multiply
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void QMUL(); void QMUL();
// [SIMD] 0x08A — XADD: SIMD Addition // [SIMD] 0x08A — XADD: SIMD Addition
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void XADD(); void XADD();
// [SIMD] 0x08B — XSUB: SIMD Subtract // [SIMD] 0x08B — XSUB: SIMD Subtract
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void XSUB(); void XSUB();
// [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add // [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void XAMA(); void XAMA();
// [SIMD] 0x08D — XMUL: SIMD Multiply // [SIMD] 0x08D — XMUL: SIMD Multiply
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void XMUL(); void XMUL();
// [SIMD] 0x08E — XDIV: SIMD Divide // [SIMD] 0x08E — XDIV: SIMD Divide
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void XDIV(); void XDIV();
// [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory // [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
// Operation: // Operation:
void UPY(); void UPY();
//[Easter Egg] 0x0F1 - LLGS: Injects the custom 8x4 ASCII spider logo
// into RAM [0x80-0x9F] and signs Register RA with the "LLGS" hex literal.
void LLGS();
// </pygen-target> // // </pygen-target> //
}; };