Simplify instruction comments and add default cases to switches

This commit is contained in:
Diego De Gante Pérez
2026-04-06 13:12:31 -06:00
parent 429596af86
commit 6fb7a23e5d
2 changed files with 22 additions and 65 deletions
+4 -16
View File
@@ -154,10 +154,7 @@ namespace spider {
// TODO: Implement JIF
}
/**
* 0x03C — Jump Relative.
* Adds a signed offset (Dst) to the instruction register.
*/
// ── 0x03C — JMR: Dst + Instruction Register -> Instruction Register ──
void CPU::JMR() {
fetchOperDst();
i64 offset;
@@ -170,10 +167,7 @@ namespace spider {
RI = static_cast<u64>(static_cast<i64>(RI) + offset);
}
/**
* 0x03D — Jump Relative if Equal.
* Adds a signed offset (Dst) to RI only if the Equal flag (bit 10) is set.
*/
// ── 0x03D — JER: Dst + Instruction Register -> Instruction Register IF Flags.EQ ──
void CPU::JER() {
fetchOperDst();
if (RF & CPU::FLAG_EQUAL) {
@@ -188,10 +182,7 @@ namespace spider {
}
}
/**
* 0x03E — Jump Relative if Not Equal.
* Adds a signed offset (Dst) to RI only if the Equal flag (bit 10) is cleared.
*/
// ── 0x03E — JNR: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ ──
void CPU::JNR() {
fetchOperDst();
if (!(RF & CPU::FLAG_EQUAL)) {
@@ -206,10 +197,7 @@ namespace spider {
}
}
/**
* 0x03F — Jump Relative if Src is true.
* Adds a signed offset (Dst) to RI only if Src is booleanly true (non-zero).
*/
// ── 0x03F — JIR: Dst + Instruction Register -> Instruction Register IF Src ──
void CPU::JIR() {
fetchOperSrc();
fetchOperDst();