Add InstrMap.cpp generation to pygen
This commit is contained in:
Diego De Gante Pérez
@@ -234,327 +234,327 @@ namespace spider {
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void MMODE();
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// [System] 0x003 — INT: Interrupt
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// Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 08
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// Operation: Performs system interrupt no. (Dst) (See table)
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void INT();
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// [System] 0x004 — LRV: Load Interrupt Vector Register
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// Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 0C
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// Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 08
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// Operation: Dst -> RV
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void LRV();
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// [System] 0x005 — FSR: Fetch System Register
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 08
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// Operation: System Register at Dst -> Dst
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void FSR();
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// [System] 0x006 — FIR: Fetch Instruction Register
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 08
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// Operation: Instruction Register -> Dst
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void FIR();
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// [System] 0x007 — FZR: Fetch Stack Base Register
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 08
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// Operation: Stack Base Register -> Dst
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void FZR();
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// [System] 0x008 — LSR: Load System Register
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// Params: 2 | AddrMask1: 1E AddrMask2: 1F | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: 1F | TypeMask: 08
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// Operation: Src -> System Register at Dst
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void LSR();
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// [System] 0x009 — FVR: Fetch Interrupt Vector Register
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// Params: 1 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: 04 AddrMask2: 00 | TypeMask: 08
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// Operation: Interrupt Vector Register -> Dst
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void FVR();
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// [Memory] 0x00A — MOV: Moves values
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// Params: 2 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src -> Dst
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void MOV();
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// [Memory] 0x00B — MOR: Moves registers
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// Params: 2 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 2 | AddrMask1: 04 AddrMask2: 04 | TypeMask: 08
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// Operation: R Scr -> R Dst
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void MOR();
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// [Memory] 0x00C — AMOV: Array Move, uses X and Y as ptrs, A as amount
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 08
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// Operation: Array from X to Y, by A amount
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void AMOV();
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// [Memory] 0x00D — SWP: Swap registers
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// Params: 2 | AddrMask1: 04 AddrMask2: 04 | TypeMask: 00
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// Params: 2 | AddrMask1: 04 AddrMask2: 04 | TypeMask: 08
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// Operation: Src <-> Dst
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void SWP();
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// [Memory] 0x00E — AHM: Ask Host for Memory
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// Params: 1 | AddrMask1: 04 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: 04 AddrMask2: 00 | TypeMask: 08
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// Operation: Asks the host for a specific size of memory. Responds with 0 or 1
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void AHM();
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// [Integer] 0x010 — COM: One's complement
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: ~ Dst -> Dst
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void COM();
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// [Integer] 0x011 — NEG: Two's complement
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: - Dst -> Dst
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void NEG();
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// [Integer] 0x012 — EXS: Extend Sign
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Last bit is copied and expanded for the next int size
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void EXS();
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// [Integer] 0x013 — INC: Increment
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + 1 -> Dst
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void INC();
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// [Integer] 0x014 — DEC: Decrement
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst - 1 -> Dst
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void DEC();
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// [Integer] 0x015 — ADD: Addition
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst + Src -> Dst
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void ADD();
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// [Integer] 0x016 — SUB: Subtraction
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst - Src-> Dst
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void SUB();
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// [Integer] 0x017 — MUL: Multiplication
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst * Src -> Dst
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void MUL();
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// [Integer] 0x018 — UMUL: Unsigned Multiplication
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst * Src -> Dst
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void UMUL();
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// [Integer] 0x019 — DIV: Division
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst / Src -> Dst
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void DIV();
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// [Integer] 0x01A — UDIV: Unsigned Division
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst / Src -> Dst
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void UDIV();
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// [Integer] 0x01B — MOD: Modulus
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst % Src -> Dst
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void MOD();
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// [Integer] 0x01C — UMOD: Unsigned Modulus
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst % Src -> Dst
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void UMOD();
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// [Integer] 0x01D — DMOD: Division and Modulus
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Signed Dst / Src -> X, Dst % Src -> Y
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void DMOD();
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// [Integer] 0x01E — UDMD: Unsigned Division and Modulus
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Unsigned Dst / Src -> X, Dst % Src -> Y
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void UDMD();
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// [System] 0x01F — FBT: Test and update Flag Register (Integer) Bits
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Flags of Dst -
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void FBT();
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// [Bit Wise] 0x020 — STB: Set Bit
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src# bit is set on Dst
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void STB();
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// [Bit Wise] 0x021 — CRB: Clear Bit
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src# bit is cleared on Dst
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void CRB();
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// [Bit Wise] 0x022 — TSB: Test Bit
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Src# bit is tested against Dst, updates Equal Flag
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void TSB();
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// [Bit Wise] 0x023 — BOOL: Sets the booleaness of a value
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Tests Dst != 0, updates Equal Flag
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void BOOL();
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// [Bit Wise] 0x024 — NOT: Sets the inverse booleaness of a value (! BOOL)
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Tests Dst == 0, updates Equal Flag
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void NOT();
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// [Bit Wise] 0x025 — AND: Boolean AND operation
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst AND Src into Dst
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void AND();
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// [Bit Wise] 0x026 — OR: Boolean OR operation
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst OR Src into Dst
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void OR();
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// [Bit Wise] 0x027 — XOR: Boolean XOR operation
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst XOR Src into Dst
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void XOR();
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// [Bit Wise] 0x028 — SHL: Arithmetic Shift Left
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst << Src into Dst
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void SHL();
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// [Bit Wise] 0x029 — SHR: Arithmetic Shift Right
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst >> Src into Dst
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void SHR();
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// [Bit Wise] 0x02A — SSR: Signed Shift Right
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst >>> Src into Dst
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void SSR();
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// [Bit Wise] 0x02B — ROL: Rotate Left
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst ROL Src into Dst
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void ROL();
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// [Bit Wise] 0x02C — ROR: Rotate Right
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst ROR Src into Dst
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void ROR();
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// [Bit Wise] 0x02D — CNT: Counts bits
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: # of 1's into Dst
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void CNT();
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// [Boolean] 0x030 — EQ: Equal
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst == Src into Dst
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void EQ();
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// [Boolean] 0x031 — NE: Not Equal
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst != Src into Dst
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void NE();
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// [Boolean] 0x032 — GT: Greater Than
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst > Src into Dst
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void GT();
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// [Boolean] 0x033 — GE: Greater or Equal Than
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst >= Src into Dst
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void GE();
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// [Boolean] 0x034 — LT: Lower Than
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst < Src into Dst
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void LT();
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// [Boolean] 0x035 — LE: Lower or Equal Than
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst <= Src into Dst
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void LE();
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// [Branch] 0x038 — JMP: Jump to absolute position
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> Instruction Register
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void JMP();
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// [Branch] 0x039 — JEQ: Jumps to position if EQ flag is set
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> Instruction Register IF Flags.EQ
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void JEQ();
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// [Branch] 0x03A — JNE: Jumps to position if EQ flag is cleared
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> Instruction Register IF NOT Flags.EQ
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void JNE();
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// [Branch] 0x03B — JIF: Jumps if value provided is booleanly true
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst -> Instruction Register IF Src
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void JIF();
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// [Branch] 0x03C — JMR: Jump Relative
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register
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void JMR();
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// [Branch] 0x03D — JER: Jumps to relative position if EQ flag is set
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register IF Flags.EQ
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void JER();
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// [Branch] 0x03E — JNR: Jumps to relative position if EQ flag is cleared
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ
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void JNR();
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// [Branch] 0x03F — JIR: Jumps to relative position if value provided is booleanly true
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation: Dst + Instruction Register -> Instruction Register IF Src
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void JIR();
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// [System] 0x040 — SFB: Store (User) Flag Bit
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void SFB();
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// [System] 0x041 — LFB: Load (User) Flag Bit
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void LFB();
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// [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void JUF();
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// [Branch] 0x043 — JUR: Jump to relative position, if user flag is true
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0F
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// Operation:
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void JUR();
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// [Memory] 0x044 — PUSH: Push to stack
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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// Operation: Dst -> pushed into stack
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void PUSH();
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// [Memory] 0x045 — POP: Pop from stack
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// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
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// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
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||||
// Operation: popped from stack -> Dst
|
||||
void POP();
|
||||
|
||||
// [Memory] 0x046 — ALLOC: Allocate to heap
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
|
||||
// Operation: Dst -> heap ptr of size Dst
|
||||
void ALLOC();
|
||||
|
||||
// [Memory] 0x047 — HFREE: Delete from heap
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
|
||||
// Operation: Frees heap ptr in Dst
|
||||
void HFREE();
|
||||
|
||||
// [Branch] 0x04A — CALL: Call function at instruction index
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
|
||||
// Operation: Performs a function call, step XX
|
||||
void CALL();
|
||||
|
||||
@@ -564,207 +564,207 @@ namespace spider {
|
||||
void RET();
|
||||
|
||||
// [System] 0x04C — EDI: Enable/Disable External Interrupts
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
|
||||
// Operation: bool( Dst ) -> Enable External Interrupts Bit
|
||||
void EDI();
|
||||
|
||||
// [System] 0x04D — SHSS: Set Hotswap Signal Bit
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0F
|
||||
// Operation: bool( Dst ) -> Hot Swap Signal Bit
|
||||
void SHSS();
|
||||
|
||||
// [Floating Point] 0x050 — FLI: Float Load Immediate
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation:
|
||||
void FLI();
|
||||
|
||||
// [Floating Point] 0x051 — FNEG: Float negate
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: - Dst -> Dst
|
||||
void FNEG();
|
||||
|
||||
// [Floating Point] 0x052 — FADD: Float add
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst + Src -> Dst
|
||||
void FADD();
|
||||
|
||||
// [Floating Point] 0x053 — FSUB: Float subtract
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst - Src-> Dst
|
||||
void FSUB();
|
||||
|
||||
// [Floating Point] 0x054 — FMUL: Float multiplication
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst * Src -> Dst
|
||||
void FMUL();
|
||||
|
||||
// [Floating Point] 0x055 — FDIV: Float division
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst / Src -> Dst
|
||||
void FDIV();
|
||||
|
||||
// [Floating Point] 0x056 — FMOD: Float modulus
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst % Src -> Dst
|
||||
void FMOD();
|
||||
|
||||
// [Floating Point] 0x057 — FDMOD: Float division and modulus
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst / Src -> X, Dst % Src -> Y
|
||||
void FDMOD();
|
||||
|
||||
// [Floating Point] 0x058 — FEPS: Sets the float epsilon value, for comparison
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: Dst -> Epsilon Register
|
||||
void FEPS();
|
||||
|
||||
// [Floating Point] 0x059 — FEEP: Float Enable/Disable Epsilon
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: bool( Dst ) -> Epsilon Enable Bit
|
||||
void FEEP();
|
||||
|
||||
// [Boolean] 0x05A — FEQ: Float Equal
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst == Src into Dst
|
||||
void FEQ();
|
||||
|
||||
// [Boolean] 0x05B — FNE: Float Not Equal
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst != Src into Dst
|
||||
void FNE();
|
||||
|
||||
// [Boolean] 0x05C — FGT: Float Greater Than
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst > Src into Dst
|
||||
void FGT();
|
||||
|
||||
// [Boolean] 0x05D — FGE: Float Greater or Equal Than
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst >= Src into Dst
|
||||
void FGE();
|
||||
|
||||
// [Boolean] 0x05E — FLT: Float Lower Than
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst < Src into Dst
|
||||
void FLT();
|
||||
|
||||
// [Boolean] 0x05F — FLE: Float Lower or Equal Than
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: Dst <= Src into Dst
|
||||
void FLE();
|
||||
|
||||
// [Casts] 0x060 — F2D: F32 (Float) to F64 (Double)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void F2D();
|
||||
|
||||
// [Casts] 0x061 — D2F: F64 (Double) to F32 (Float)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void D2F();
|
||||
|
||||
// [Casts] 0x062 — I2F: I32 (Integer) to F32 (Float)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void I2F();
|
||||
|
||||
// [Casts] 0x063 — I2D: I32 (Integer) to F64 (Double)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void I2D();
|
||||
|
||||
// [Casts] 0x064 — L2F: I64 (Long) to F32 (Float)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void L2F();
|
||||
|
||||
// [Casts] 0x065 — L2D: I64 (Long) to F64 (Double)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void L2D();
|
||||
|
||||
// [Casts] 0x066 — F2I: F32 (Float) to I32 (Integer)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void F2I();
|
||||
|
||||
// [Casts] 0x067 — F2L: F32 (Float) to I64 (Long)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void F2L();
|
||||
|
||||
// [Casts] 0x068 — D2I: F64 (Double) to I32 (Integer)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void D2I();
|
||||
|
||||
// [Casts] 0x069 — D2L: F64 (Double) to I64 (Long)
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 00
|
||||
// Operation: (cast) Dst -> Dst
|
||||
void D2L();
|
||||
|
||||
// [Trigonometric] 0x06C — SIN: Sine Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: sin( Dst ) -> Dst
|
||||
void SIN();
|
||||
|
||||
// [Trigonometric] 0x06D — COS: Cosine Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: cos( Dst ) -> Dst
|
||||
void COS();
|
||||
|
||||
// [Trigonometric] 0x06E — TAN: Tangent Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: tan( Dst ) -> Dst
|
||||
void TAN();
|
||||
|
||||
// [Trigonometric] 0x06F — ASIN: Arc Sine Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: asin( Dst ) -> Dst
|
||||
void ASIN();
|
||||
|
||||
// [Trigonometric] 0x070 — ACOS: Arc Cosine Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: acos( Dst ) -> Dst
|
||||
void ACOS();
|
||||
|
||||
// [Trigonometric] 0x071 — ATAN: Arc Tangent Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: atan( Dst ) -> Dst
|
||||
void ATAN();
|
||||
|
||||
// [Trigonometric] 0x072 — ATAN2: Arc Tangent Function with 2 Arguments
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: atan( Dst, Src ) -> Dst
|
||||
void ATAN2();
|
||||
|
||||
// [Exponential] 0x074 — EXP: Exponential Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: exp( Dst ) -> Dst
|
||||
void EXP();
|
||||
|
||||
// [Exponential] 0x075 — LOG: Natural Logarithm
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: ln( Dst ) -> Dst
|
||||
void LOG();
|
||||
|
||||
// [Exponential] 0x076 — LOGAB: Logarithm A of B
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: log( Dst, Src ) -> Dst
|
||||
void LOGAB();
|
||||
|
||||
// [Exponential] 0x077 — POW: Power Function
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: pow( Dst, Src ) -> Dst
|
||||
void POW();
|
||||
|
||||
// [Exponential] 0x078 — SQRT: Square Root
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 1 | AddrMask1: FF AddrMask2: 00 | TypeMask: 0C
|
||||
// Operation: sqrt( Dst ) -> Dst
|
||||
void SQRT();
|
||||
|
||||
// [Exponential] 0x079 — ROOT: General Root
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Params: 2 | AddrMask1: 1E AddrMask2: FF | TypeMask: 0C
|
||||
// Operation: pow( Dst, 1 / Src ) -> Dst
|
||||
void ROOT();
|
||||
|
||||
@@ -818,6 +818,16 @@ namespace spider {
|
||||
// Operation:
|
||||
void MDET();
|
||||
|
||||
// [Quaternion] 0x086 — QMKA: Quaternion Make from Angles
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Operation:
|
||||
void QMKA();
|
||||
|
||||
// [Quaternion] 0x087 — QMUL: Quaternion Multiply
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Operation:
|
||||
void QMUL();
|
||||
|
||||
// [SIMD] 0x08A — XADD: SIMD Addition
|
||||
// Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00
|
||||
// Operation:
|
||||
|
||||
748
src/spider/runtime/cpu/InstrMap.cpp
Normal file
748
src/spider/runtime/cpu/InstrMap.cpp
Normal file
@@ -0,0 +1,748 @@
|
||||
/**
|
||||
* @file InstrMap.cpp
|
||||
* @brief Spider VM instruction dispatch — array and switch implementations.
|
||||
*
|
||||
* AUTO-GENERATED by pygen.ipynb — DO NOT EDIT BY HAND.
|
||||
*
|
||||
* This file provides two equivalent dispatch mechanisms:
|
||||
*
|
||||
* 1. InstrMap[] — A lookup table of member-function pointers indexed by
|
||||
* opcode. O(1) dispatch; suitable for platforms where
|
||||
* indirect calls through function pointers are efficient.
|
||||
*
|
||||
* 2. CPU::execute(u16) — A switch/case over every opcode. Lets the
|
||||
* compiler emit a jump table or branch tree; may be
|
||||
* preferable on microcontrollers or when link-time
|
||||
* optimisation can inline the handlers.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "CPU.hpp"
|
||||
|
||||
namespace spider {
|
||||
|
||||
// =============================================================
|
||||
// Version 1 — Lookup table of member-function pointers
|
||||
// =============================================================
|
||||
|
||||
/** Pointer-to-member type for a zero-argument CPU instruction. */
|
||||
using CPUInstr = void (CPU::*)();
|
||||
|
||||
/**
|
||||
* Instruction dispatch table (512 entries, 9-bit opcode space).
|
||||
*
|
||||
* Usage:
|
||||
* u16 opcode = fetch();
|
||||
* CPUInstr fn = InstrMap[opcode];
|
||||
* if (fn) (cpu.*fn)();
|
||||
*/
|
||||
CPUInstr InstrMap[512] = {
|
||||
&CPU::NOP, // 0x000 — No Operation
|
||||
&CPU::SPDR, // 0x001 — Will place the Spider version of the interpreter in RA
|
||||
&CPU::MMODE, // 0x002 — Set Memory Mode
|
||||
&CPU::INT, // 0x003 — Interrupt
|
||||
&CPU::LRV, // 0x004 — Load Interrupt Vector Register
|
||||
&CPU::FSR, // 0x005 — Fetch System Register
|
||||
&CPU::FIR, // 0x006 — Fetch Instruction Register
|
||||
&CPU::FZR, // 0x007 — Fetch Stack Base Register
|
||||
&CPU::LSR, // 0x008 — Load System Register
|
||||
&CPU::FVR, // 0x009 — Fetch Interrupt Vector Register
|
||||
&CPU::MOV, // 0x00A — Moves values
|
||||
&CPU::MOR, // 0x00B — Moves registers
|
||||
&CPU::AMOV, // 0x00C — Array Move, uses X and Y as ptrs, A as amount
|
||||
&CPU::SWP, // 0x00D — Swap registers
|
||||
&CPU::AHM, // 0x00E — Ask Host for Memory
|
||||
nullptr, // 0x00F (reserved)
|
||||
&CPU::COM, // 0x010 — One's complement
|
||||
&CPU::NEG, // 0x011 — Two's complement
|
||||
&CPU::EXS, // 0x012 — Extend Sign
|
||||
&CPU::INC, // 0x013 — Increment
|
||||
&CPU::DEC, // 0x014 — Decrement
|
||||
&CPU::ADD, // 0x015 — Addition
|
||||
&CPU::SUB, // 0x016 — Subtraction
|
||||
&CPU::MUL, // 0x017 — Multiplication
|
||||
&CPU::UMUL, // 0x018 — Unsigned Multiplication
|
||||
&CPU::DIV, // 0x019 — Division
|
||||
&CPU::UDIV, // 0x01A — Unsigned Division
|
||||
&CPU::MOD, // 0x01B — Modulus
|
||||
&CPU::UMOD, // 0x01C — Unsigned Modulus
|
||||
&CPU::DMOD, // 0x01D — Division and Modulus
|
||||
&CPU::UDMD, // 0x01E — Unsigned Division and Modulus
|
||||
&CPU::FBT, // 0x01F — Test and update Flag Register (Integer) Bits
|
||||
&CPU::STB, // 0x020 — Set Bit
|
||||
&CPU::CRB, // 0x021 — Clear Bit
|
||||
&CPU::TSB, // 0x022 — Test Bit
|
||||
&CPU::BOOL, // 0x023 — Sets the booleaness of a value
|
||||
&CPU::NOT, // 0x024 — Sets the inverse booleaness of a value (! BOOL)
|
||||
&CPU::AND, // 0x025 — Boolean AND operation
|
||||
&CPU::OR, // 0x026 — Boolean OR operation
|
||||
&CPU::XOR, // 0x027 — Boolean XOR operation
|
||||
&CPU::SHL, // 0x028 — Arithmetic Shift Left
|
||||
&CPU::SHR, // 0x029 — Arithmetic Shift Right
|
||||
&CPU::SSR, // 0x02A — Signed Shift Right
|
||||
&CPU::ROL, // 0x02B — Rotate Left
|
||||
&CPU::ROR, // 0x02C — Rotate Right
|
||||
&CPU::CNT, // 0x02D — Counts bits
|
||||
nullptr, // 0x02E (reserved)
|
||||
nullptr, // 0x02F (reserved)
|
||||
&CPU::EQ, // 0x030 — Equal
|
||||
&CPU::NE, // 0x031 — Not Equal
|
||||
&CPU::GT, // 0x032 — Greater Than
|
||||
&CPU::GE, // 0x033 — Greater or Equal Than
|
||||
&CPU::LT, // 0x034 — Lower Than
|
||||
&CPU::LE, // 0x035 — Lower or Equal Than
|
||||
nullptr, // 0x036 (reserved)
|
||||
nullptr, // 0x037 (reserved)
|
||||
&CPU::JMP, // 0x038 — Jump to absolute position
|
||||
&CPU::JEQ, // 0x039 — Jumps to position if EQ flag is set
|
||||
&CPU::JNE, // 0x03A — Jumps to position if EQ flag is cleared
|
||||
&CPU::JIF, // 0x03B — Jumps if value provided is booleanly true
|
||||
&CPU::JMR, // 0x03C — Jump Relative
|
||||
&CPU::JER, // 0x03D — Jumps to relative position if EQ flag is set
|
||||
&CPU::JNR, // 0x03E — Jumps to relative position if EQ flag is cleared
|
||||
&CPU::JIR, // 0x03F — Jumps to relative position if value provided is booleanly true
|
||||
&CPU::SFB, // 0x040 — Store (User) Flag Bit
|
||||
&CPU::LFB, // 0x041 — Load (User) Flag Bit
|
||||
&CPU::JUF, // 0x042 — Jump to absolute position, if user flag is true
|
||||
&CPU::JUR, // 0x043 — Jump to relative position, if user flag is true
|
||||
&CPU::PUSH, // 0x044 — Push to stack
|
||||
&CPU::POP, // 0x045 — Pop from stack
|
||||
&CPU::ALLOC, // 0x046 — Allocate to heap
|
||||
&CPU::HFREE, // 0x047 — Delete from heap
|
||||
nullptr, // 0x048 (reserved)
|
||||
nullptr, // 0x049 (reserved)
|
||||
&CPU::CALL, // 0x04A — Call function at instruction index
|
||||
&CPU::RET, // 0x04B — Return from a function
|
||||
&CPU::EDI, // 0x04C — Enable/Disable External Interrupts
|
||||
&CPU::SHSS, // 0x04D — Set Hotswap Signal Bit
|
||||
nullptr, // 0x04E (reserved)
|
||||
nullptr, // 0x04F (reserved)
|
||||
&CPU::FLI, // 0x050 — Float Load Immediate
|
||||
&CPU::FNEG, // 0x051 — Float negate
|
||||
&CPU::FADD, // 0x052 — Float add
|
||||
&CPU::FSUB, // 0x053 — Float subtract
|
||||
&CPU::FMUL, // 0x054 — Float multiplication
|
||||
&CPU::FDIV, // 0x055 — Float division
|
||||
&CPU::FMOD, // 0x056 — Float modulus
|
||||
&CPU::FDMOD, // 0x057 — Float division and modulus
|
||||
&CPU::FEPS, // 0x058 — Sets the float epsilon value, for comparison
|
||||
&CPU::FEEP, // 0x059 — Float Enable/Disable Epsilon
|
||||
&CPU::FEQ, // 0x05A — Float Equal
|
||||
&CPU::FNE, // 0x05B — Float Not Equal
|
||||
&CPU::FGT, // 0x05C — Float Greater Than
|
||||
&CPU::FGE, // 0x05D — Float Greater or Equal Than
|
||||
&CPU::FLT, // 0x05E — Float Lower Than
|
||||
&CPU::FLE, // 0x05F — Float Lower or Equal Than
|
||||
&CPU::F2D, // 0x060 — F32 (Float) to F64 (Double)
|
||||
&CPU::D2F, // 0x061 — F64 (Double) to F32 (Float)
|
||||
&CPU::I2F, // 0x062 — I32 (Integer) to F32 (Float)
|
||||
&CPU::I2D, // 0x063 — I32 (Integer) to F64 (Double)
|
||||
&CPU::L2F, // 0x064 — I64 (Long) to F32 (Float)
|
||||
&CPU::L2D, // 0x065 — I64 (Long) to F64 (Double)
|
||||
&CPU::F2I, // 0x066 — F32 (Float) to I32 (Integer)
|
||||
&CPU::F2L, // 0x067 — F32 (Float) to I64 (Long)
|
||||
&CPU::D2I, // 0x068 — F64 (Double) to I32 (Integer)
|
||||
&CPU::D2L, // 0x069 — F64 (Double) to I64 (Long)
|
||||
nullptr, // 0x06A (reserved)
|
||||
nullptr, // 0x06B (reserved)
|
||||
&CPU::SIN, // 0x06C — Sine Function
|
||||
&CPU::COS, // 0x06D — Cosine Function
|
||||
&CPU::TAN, // 0x06E — Tangent Function
|
||||
&CPU::ASIN, // 0x06F — Arc Sine Function
|
||||
&CPU::ACOS, // 0x070 — Arc Cosine Function
|
||||
&CPU::ATAN, // 0x071 — Arc Tangent Function
|
||||
&CPU::ATAN2, // 0x072 — Arc Tangent Function with 2 Arguments
|
||||
nullptr, // 0x073 (reserved)
|
||||
&CPU::EXP, // 0x074 — Exponential Function
|
||||
&CPU::LOG, // 0x075 — Natural Logarithm
|
||||
&CPU::LOGAB, // 0x076 — Logarithm A of B
|
||||
&CPU::POW, // 0x077 — Power Function
|
||||
&CPU::SQRT, // 0x078 — Square Root
|
||||
&CPU::ROOT, // 0x079 — General Root
|
||||
nullptr, // 0x07A (reserved)
|
||||
nullptr, // 0x07B (reserved)
|
||||
&CPU::ADC, // 0x07C — Add with Carry
|
||||
&CPU::SWC, // 0x07D — Subtract with Carry (Borrow)
|
||||
&CPU::MWO, // 0x07E — Multiply with Overflow
|
||||
&CPU::UMO, // 0x07F — Unsigned Multiply with Overflow
|
||||
&CPU::MADD, // 0x080 — Matrix Addition
|
||||
&CPU::MSUB, // 0x081 — Matrix Subtraction
|
||||
&CPU::MMUL, // 0x082 — Matrix Multiply
|
||||
&CPU::MINV, // 0x083 — Matrix Inverse
|
||||
&CPU::MTRA, // 0x084 — Matrix Transpose
|
||||
&CPU::MDET, // 0x085 — Matrix Determinant
|
||||
&CPU::QMKA, // 0x086 — Quaternion Make from Angles
|
||||
&CPU::QMUL, // 0x087 — Quaternion Multiply
|
||||
nullptr, // 0x088
|
||||
nullptr, // 0x089
|
||||
&CPU::XADD, // 0x08A — SIMD Addition
|
||||
&CPU::XSUB, // 0x08B — SIMD Subtract
|
||||
&CPU::XAMA, // 0x08C — SIMD Alternate Multiply-Add
|
||||
&CPU::XMUL, // 0x08D — SIMD Multiply
|
||||
&CPU::XDIV, // 0x08E — SIMD Divide
|
||||
nullptr, // 0x08F
|
||||
nullptr, // 0x090
|
||||
nullptr, // 0x091
|
||||
nullptr, // 0x092
|
||||
nullptr, // 0x093
|
||||
nullptr, // 0x094
|
||||
nullptr, // 0x095
|
||||
nullptr, // 0x096
|
||||
nullptr, // 0x097
|
||||
nullptr, // 0x098
|
||||
nullptr, // 0x099
|
||||
nullptr, // 0x09A
|
||||
nullptr, // 0x09B
|
||||
nullptr, // 0x09C
|
||||
nullptr, // 0x09D
|
||||
nullptr, // 0x09E
|
||||
nullptr, // 0x09F
|
||||
nullptr, // 0x0A0
|
||||
nullptr, // 0x0A1
|
||||
nullptr, // 0x0A2
|
||||
nullptr, // 0x0A3
|
||||
nullptr, // 0x0A4
|
||||
nullptr, // 0x0A5
|
||||
nullptr, // 0x0A6
|
||||
nullptr, // 0x0A7
|
||||
nullptr, // 0x0A8
|
||||
nullptr, // 0x0A9
|
||||
nullptr, // 0x0AA
|
||||
nullptr, // 0x0AB
|
||||
nullptr, // 0x0AC
|
||||
nullptr, // 0x0AD
|
||||
nullptr, // 0x0AE
|
||||
nullptr, // 0x0AF
|
||||
nullptr, // 0x0B0
|
||||
nullptr, // 0x0B1
|
||||
nullptr, // 0x0B2
|
||||
nullptr, // 0x0B3
|
||||
nullptr, // 0x0B4
|
||||
nullptr, // 0x0B5
|
||||
nullptr, // 0x0B6
|
||||
nullptr, // 0x0B7
|
||||
nullptr, // 0x0B8
|
||||
nullptr, // 0x0B9
|
||||
nullptr, // 0x0BA
|
||||
nullptr, // 0x0BB
|
||||
nullptr, // 0x0BC
|
||||
nullptr, // 0x0BD
|
||||
nullptr, // 0x0BE
|
||||
nullptr, // 0x0BF
|
||||
nullptr, // 0x0C0
|
||||
nullptr, // 0x0C1
|
||||
nullptr, // 0x0C2
|
||||
nullptr, // 0x0C3
|
||||
nullptr, // 0x0C4
|
||||
nullptr, // 0x0C5
|
||||
nullptr, // 0x0C6
|
||||
nullptr, // 0x0C7
|
||||
nullptr, // 0x0C8
|
||||
nullptr, // 0x0C9
|
||||
nullptr, // 0x0CA
|
||||
nullptr, // 0x0CB
|
||||
nullptr, // 0x0CC
|
||||
nullptr, // 0x0CD
|
||||
nullptr, // 0x0CE
|
||||
nullptr, // 0x0CF
|
||||
nullptr, // 0x0D0
|
||||
nullptr, // 0x0D1
|
||||
nullptr, // 0x0D2
|
||||
nullptr, // 0x0D3
|
||||
nullptr, // 0x0D4
|
||||
nullptr, // 0x0D5
|
||||
nullptr, // 0x0D6
|
||||
nullptr, // 0x0D7
|
||||
nullptr, // 0x0D8
|
||||
nullptr, // 0x0D9
|
||||
nullptr, // 0x0DA
|
||||
nullptr, // 0x0DB
|
||||
nullptr, // 0x0DC
|
||||
nullptr, // 0x0DD
|
||||
nullptr, // 0x0DE
|
||||
nullptr, // 0x0DF
|
||||
nullptr, // 0x0E0
|
||||
nullptr, // 0x0E1
|
||||
nullptr, // 0x0E2
|
||||
nullptr, // 0x0E3
|
||||
nullptr, // 0x0E4
|
||||
nullptr, // 0x0E5
|
||||
nullptr, // 0x0E6
|
||||
nullptr, // 0x0E7
|
||||
nullptr, // 0x0E8
|
||||
nullptr, // 0x0E9
|
||||
nullptr, // 0x0EA
|
||||
nullptr, // 0x0EB
|
||||
nullptr, // 0x0EC
|
||||
nullptr, // 0x0ED
|
||||
nullptr, // 0x0EE
|
||||
nullptr, // 0x0EF
|
||||
&CPU::UPY, // 0x0F0 — Will place "YUPI" in memory
|
||||
nullptr, // 0x0F1
|
||||
nullptr, // 0x0F2
|
||||
nullptr, // 0x0F3
|
||||
nullptr, // 0x0F4
|
||||
nullptr, // 0x0F5
|
||||
nullptr, // 0x0F6
|
||||
nullptr, // 0x0F7
|
||||
nullptr, // 0x0F8
|
||||
nullptr, // 0x0F9
|
||||
nullptr, // 0x0FA
|
||||
nullptr, // 0x0FB
|
||||
nullptr, // 0x0FC
|
||||
nullptr, // 0x0FD
|
||||
nullptr, // 0x0FE
|
||||
nullptr, // 0x0FF
|
||||
nullptr, // 0x100
|
||||
nullptr, // 0x101
|
||||
nullptr, // 0x102
|
||||
nullptr, // 0x103
|
||||
nullptr, // 0x104
|
||||
nullptr, // 0x105
|
||||
nullptr, // 0x106
|
||||
nullptr, // 0x107
|
||||
nullptr, // 0x108
|
||||
nullptr, // 0x109
|
||||
nullptr, // 0x10A
|
||||
nullptr, // 0x10B
|
||||
nullptr, // 0x10C
|
||||
nullptr, // 0x10D
|
||||
nullptr, // 0x10E
|
||||
nullptr, // 0x10F
|
||||
nullptr, // 0x110
|
||||
nullptr, // 0x111
|
||||
nullptr, // 0x112
|
||||
nullptr, // 0x113
|
||||
nullptr, // 0x114
|
||||
nullptr, // 0x115
|
||||
nullptr, // 0x116
|
||||
nullptr, // 0x117
|
||||
nullptr, // 0x118
|
||||
nullptr, // 0x119
|
||||
nullptr, // 0x11A
|
||||
nullptr, // 0x11B
|
||||
nullptr, // 0x11C
|
||||
nullptr, // 0x11D
|
||||
nullptr, // 0x11E
|
||||
nullptr, // 0x11F
|
||||
nullptr, // 0x120
|
||||
nullptr, // 0x121
|
||||
nullptr, // 0x122
|
||||
nullptr, // 0x123
|
||||
nullptr, // 0x124
|
||||
nullptr, // 0x125
|
||||
nullptr, // 0x126
|
||||
nullptr, // 0x127
|
||||
nullptr, // 0x128
|
||||
nullptr, // 0x129
|
||||
nullptr, // 0x12A
|
||||
nullptr, // 0x12B
|
||||
nullptr, // 0x12C
|
||||
nullptr, // 0x12D
|
||||
nullptr, // 0x12E
|
||||
nullptr, // 0x12F
|
||||
nullptr, // 0x130
|
||||
nullptr, // 0x131
|
||||
nullptr, // 0x132
|
||||
nullptr, // 0x133
|
||||
nullptr, // 0x134
|
||||
nullptr, // 0x135
|
||||
nullptr, // 0x136
|
||||
nullptr, // 0x137
|
||||
nullptr, // 0x138
|
||||
nullptr, // 0x139
|
||||
nullptr, // 0x13A
|
||||
nullptr, // 0x13B
|
||||
nullptr, // 0x13C
|
||||
nullptr, // 0x13D
|
||||
nullptr, // 0x13E
|
||||
nullptr, // 0x13F
|
||||
nullptr, // 0x140
|
||||
nullptr, // 0x141
|
||||
nullptr, // 0x142
|
||||
nullptr, // 0x143
|
||||
nullptr, // 0x144
|
||||
nullptr, // 0x145
|
||||
nullptr, // 0x146
|
||||
nullptr, // 0x147
|
||||
nullptr, // 0x148
|
||||
nullptr, // 0x149
|
||||
nullptr, // 0x14A
|
||||
nullptr, // 0x14B
|
||||
nullptr, // 0x14C
|
||||
nullptr, // 0x14D
|
||||
nullptr, // 0x14E
|
||||
nullptr, // 0x14F
|
||||
nullptr, // 0x150
|
||||
nullptr, // 0x151
|
||||
nullptr, // 0x152
|
||||
nullptr, // 0x153
|
||||
nullptr, // 0x154
|
||||
nullptr, // 0x155
|
||||
nullptr, // 0x156
|
||||
nullptr, // 0x157
|
||||
nullptr, // 0x158
|
||||
nullptr, // 0x159
|
||||
nullptr, // 0x15A
|
||||
nullptr, // 0x15B
|
||||
nullptr, // 0x15C
|
||||
nullptr, // 0x15D
|
||||
nullptr, // 0x15E
|
||||
nullptr, // 0x15F
|
||||
nullptr, // 0x160
|
||||
nullptr, // 0x161
|
||||
nullptr, // 0x162
|
||||
nullptr, // 0x163
|
||||
nullptr, // 0x164
|
||||
nullptr, // 0x165
|
||||
nullptr, // 0x166
|
||||
nullptr, // 0x167
|
||||
nullptr, // 0x168
|
||||
nullptr, // 0x169
|
||||
nullptr, // 0x16A
|
||||
nullptr, // 0x16B
|
||||
nullptr, // 0x16C
|
||||
nullptr, // 0x16D
|
||||
nullptr, // 0x16E
|
||||
nullptr, // 0x16F
|
||||
nullptr, // 0x170
|
||||
nullptr, // 0x171
|
||||
nullptr, // 0x172
|
||||
nullptr, // 0x173
|
||||
nullptr, // 0x174
|
||||
nullptr, // 0x175
|
||||
nullptr, // 0x176
|
||||
nullptr, // 0x177
|
||||
nullptr, // 0x178
|
||||
nullptr, // 0x179
|
||||
nullptr, // 0x17A
|
||||
nullptr, // 0x17B
|
||||
nullptr, // 0x17C
|
||||
nullptr, // 0x17D
|
||||
nullptr, // 0x17E
|
||||
nullptr, // 0x17F
|
||||
nullptr, // 0x180
|
||||
nullptr, // 0x181
|
||||
nullptr, // 0x182
|
||||
nullptr, // 0x183
|
||||
nullptr, // 0x184
|
||||
nullptr, // 0x185
|
||||
nullptr, // 0x186
|
||||
nullptr, // 0x187
|
||||
nullptr, // 0x188
|
||||
nullptr, // 0x189
|
||||
nullptr, // 0x18A
|
||||
nullptr, // 0x18B
|
||||
nullptr, // 0x18C
|
||||
nullptr, // 0x18D
|
||||
nullptr, // 0x18E
|
||||
nullptr, // 0x18F
|
||||
nullptr, // 0x190
|
||||
nullptr, // 0x191
|
||||
nullptr, // 0x192
|
||||
nullptr, // 0x193
|
||||
nullptr, // 0x194
|
||||
nullptr, // 0x195
|
||||
nullptr, // 0x196
|
||||
nullptr, // 0x197
|
||||
nullptr, // 0x198
|
||||
nullptr, // 0x199
|
||||
nullptr, // 0x19A
|
||||
nullptr, // 0x19B
|
||||
nullptr, // 0x19C
|
||||
nullptr, // 0x19D
|
||||
nullptr, // 0x19E
|
||||
nullptr, // 0x19F
|
||||
nullptr, // 0x1A0
|
||||
nullptr, // 0x1A1
|
||||
nullptr, // 0x1A2
|
||||
nullptr, // 0x1A3
|
||||
nullptr, // 0x1A4
|
||||
nullptr, // 0x1A5
|
||||
nullptr, // 0x1A6
|
||||
nullptr, // 0x1A7
|
||||
nullptr, // 0x1A8
|
||||
nullptr, // 0x1A9
|
||||
nullptr, // 0x1AA
|
||||
nullptr, // 0x1AB
|
||||
nullptr, // 0x1AC
|
||||
nullptr, // 0x1AD
|
||||
nullptr, // 0x1AE
|
||||
nullptr, // 0x1AF
|
||||
nullptr, // 0x1B0
|
||||
nullptr, // 0x1B1
|
||||
nullptr, // 0x1B2
|
||||
nullptr, // 0x1B3
|
||||
nullptr, // 0x1B4
|
||||
nullptr, // 0x1B5
|
||||
nullptr, // 0x1B6
|
||||
nullptr, // 0x1B7
|
||||
nullptr, // 0x1B8
|
||||
nullptr, // 0x1B9
|
||||
nullptr, // 0x1BA
|
||||
nullptr, // 0x1BB
|
||||
nullptr, // 0x1BC
|
||||
nullptr, // 0x1BD
|
||||
nullptr, // 0x1BE
|
||||
nullptr, // 0x1BF
|
||||
nullptr, // 0x1C0
|
||||
nullptr, // 0x1C1
|
||||
nullptr, // 0x1C2
|
||||
nullptr, // 0x1C3
|
||||
nullptr, // 0x1C4
|
||||
nullptr, // 0x1C5
|
||||
nullptr, // 0x1C6
|
||||
nullptr, // 0x1C7
|
||||
nullptr, // 0x1C8
|
||||
nullptr, // 0x1C9
|
||||
nullptr, // 0x1CA
|
||||
nullptr, // 0x1CB
|
||||
nullptr, // 0x1CC
|
||||
nullptr, // 0x1CD
|
||||
nullptr, // 0x1CE
|
||||
nullptr, // 0x1CF
|
||||
nullptr, // 0x1D0
|
||||
nullptr, // 0x1D1
|
||||
nullptr, // 0x1D2
|
||||
nullptr, // 0x1D3
|
||||
nullptr, // 0x1D4
|
||||
nullptr, // 0x1D5
|
||||
nullptr, // 0x1D6
|
||||
nullptr, // 0x1D7
|
||||
nullptr, // 0x1D8
|
||||
nullptr, // 0x1D9
|
||||
nullptr, // 0x1DA
|
||||
nullptr, // 0x1DB
|
||||
nullptr, // 0x1DC
|
||||
nullptr, // 0x1DD
|
||||
nullptr, // 0x1DE
|
||||
nullptr, // 0x1DF
|
||||
nullptr, // 0x1E0
|
||||
nullptr, // 0x1E1
|
||||
nullptr, // 0x1E2
|
||||
nullptr, // 0x1E3
|
||||
nullptr, // 0x1E4
|
||||
nullptr, // 0x1E5
|
||||
nullptr, // 0x1E6
|
||||
nullptr, // 0x1E7
|
||||
nullptr, // 0x1E8
|
||||
nullptr, // 0x1E9
|
||||
nullptr, // 0x1EA
|
||||
nullptr, // 0x1EB
|
||||
nullptr, // 0x1EC
|
||||
nullptr, // 0x1ED
|
||||
nullptr, // 0x1EE
|
||||
nullptr, // 0x1EF
|
||||
nullptr, // 0x1F0
|
||||
nullptr, // 0x1F1
|
||||
nullptr, // 0x1F2
|
||||
nullptr, // 0x1F3
|
||||
nullptr, // 0x1F4
|
||||
nullptr, // 0x1F5
|
||||
nullptr, // 0x1F6
|
||||
nullptr, // 0x1F7
|
||||
nullptr, // 0x1F8
|
||||
nullptr, // 0x1F9
|
||||
nullptr, // 0x1FA
|
||||
nullptr, // 0x1FB
|
||||
nullptr, // 0x1FC
|
||||
nullptr, // 0x1FD
|
||||
nullptr, // 0x1FE
|
||||
nullptr, // 0x1FF
|
||||
};
|
||||
|
||||
|
||||
// =============================================================
|
||||
// Version 2 — Switch dispatch
|
||||
// =============================================================
|
||||
|
||||
/**
|
||||
* Execute the instruction identified by @p opcode.
|
||||
*
|
||||
* This is functionally equivalent to the InstrMap[] table above
|
||||
* but expressed as a switch so the compiler can choose the best
|
||||
* lowering strategy (jump table, binary search, etc.).
|
||||
*
|
||||
* @param opcode 9-bit instruction opcode (0x000 – 0x1FF).
|
||||
*/
|
||||
void CPU::execute(u16 opcode) {
|
||||
switch (opcode) {
|
||||
|
||||
// ── System ──────────────────────────────────────
|
||||
case 0x000: NOP(); break;
|
||||
case 0x001: SPDR(); break;
|
||||
case 0x002: MMODE(); break;
|
||||
case 0x003: INT(); break;
|
||||
case 0x004: LRV(); break;
|
||||
case 0x005: FSR(); break;
|
||||
case 0x006: FIR(); break;
|
||||
case 0x007: FZR(); break;
|
||||
case 0x008: LSR(); break;
|
||||
case 0x009: FVR(); break;
|
||||
|
||||
// ── Memory ──────────────────────────────────────
|
||||
case 0x00A: MOV(); break;
|
||||
case 0x00B: MOR(); break;
|
||||
case 0x00C: AMOV(); break;
|
||||
case 0x00D: SWP(); break;
|
||||
case 0x00E: AHM(); break;
|
||||
|
||||
// ── Integer ─────────────────────────────────────
|
||||
case 0x010: COM(); break;
|
||||
case 0x011: NEG(); break;
|
||||
case 0x012: EXS(); break;
|
||||
case 0x013: INC(); break;
|
||||
case 0x014: DEC(); break;
|
||||
case 0x015: ADD(); break;
|
||||
case 0x016: SUB(); break;
|
||||
case 0x017: MUL(); break;
|
||||
case 0x018: UMUL(); break;
|
||||
case 0x019: DIV(); break;
|
||||
case 0x01A: UDIV(); break;
|
||||
case 0x01B: MOD(); break;
|
||||
case 0x01C: UMOD(); break;
|
||||
case 0x01D: DMOD(); break;
|
||||
case 0x01E: UDMD(); break;
|
||||
|
||||
// ── System ──────────────────────────────────────
|
||||
case 0x01F: FBT(); break;
|
||||
|
||||
// ── Bit Wise ────────────────────────────────────
|
||||
case 0x020: STB(); break;
|
||||
case 0x021: CRB(); break;
|
||||
case 0x022: TSB(); break;
|
||||
case 0x023: BOOL(); break;
|
||||
case 0x024: NOT(); break;
|
||||
case 0x025: AND(); break;
|
||||
case 0x026: OR(); break;
|
||||
case 0x027: XOR(); break;
|
||||
case 0x028: SHL(); break;
|
||||
case 0x029: SHR(); break;
|
||||
case 0x02A: SSR(); break;
|
||||
case 0x02B: ROL(); break;
|
||||
case 0x02C: ROR(); break;
|
||||
case 0x02D: CNT(); break;
|
||||
|
||||
// ── Boolean ─────────────────────────────────────
|
||||
case 0x030: EQ(); break;
|
||||
case 0x031: NE(); break;
|
||||
case 0x032: GT(); break;
|
||||
case 0x033: GE(); break;
|
||||
case 0x034: LT(); break;
|
||||
case 0x035: LE(); break;
|
||||
|
||||
// ── Branch ──────────────────────────────────────
|
||||
case 0x038: JMP(); break;
|
||||
case 0x039: JEQ(); break;
|
||||
case 0x03A: JNE(); break;
|
||||
case 0x03B: JIF(); break;
|
||||
case 0x03C: JMR(); break;
|
||||
case 0x03D: JER(); break;
|
||||
case 0x03E: JNR(); break;
|
||||
case 0x03F: JIR(); break;
|
||||
|
||||
// ── System ──────────────────────────────────────
|
||||
case 0x040: SFB(); break;
|
||||
case 0x041: LFB(); break;
|
||||
|
||||
// ── Branch ──────────────────────────────────────
|
||||
case 0x042: JUF(); break;
|
||||
case 0x043: JUR(); break;
|
||||
|
||||
// ── Memory ──────────────────────────────────────
|
||||
case 0x044: PUSH(); break;
|
||||
case 0x045: POP(); break;
|
||||
case 0x046: ALLOC(); break;
|
||||
case 0x047: HFREE(); break;
|
||||
|
||||
// ── Branch ──────────────────────────────────────
|
||||
case 0x04A: CALL(); break;
|
||||
case 0x04B: RET(); break;
|
||||
|
||||
// ── System ──────────────────────────────────────
|
||||
case 0x04C: EDI(); break;
|
||||
case 0x04D: SHSS(); break;
|
||||
|
||||
// ── Floating Point ──────────────────────────────
|
||||
case 0x050: FLI(); break;
|
||||
case 0x051: FNEG(); break;
|
||||
case 0x052: FADD(); break;
|
||||
case 0x053: FSUB(); break;
|
||||
case 0x054: FMUL(); break;
|
||||
case 0x055: FDIV(); break;
|
||||
case 0x056: FMOD(); break;
|
||||
case 0x057: FDMOD(); break;
|
||||
case 0x058: FEPS(); break;
|
||||
case 0x059: FEEP(); break;
|
||||
|
||||
// ── Boolean ─────────────────────────────────────
|
||||
case 0x05A: FEQ(); break;
|
||||
case 0x05B: FNE(); break;
|
||||
case 0x05C: FGT(); break;
|
||||
case 0x05D: FGE(); break;
|
||||
case 0x05E: FLT(); break;
|
||||
case 0x05F: FLE(); break;
|
||||
|
||||
// ── Casts ───────────────────────────────────────
|
||||
case 0x060: F2D(); break;
|
||||
case 0x061: D2F(); break;
|
||||
case 0x062: I2F(); break;
|
||||
case 0x063: I2D(); break;
|
||||
case 0x064: L2F(); break;
|
||||
case 0x065: L2D(); break;
|
||||
case 0x066: F2I(); break;
|
||||
case 0x067: F2L(); break;
|
||||
case 0x068: D2I(); break;
|
||||
case 0x069: D2L(); break;
|
||||
|
||||
// ── Trigonometric ───────────────────────────────
|
||||
case 0x06C: SIN(); break;
|
||||
case 0x06D: COS(); break;
|
||||
case 0x06E: TAN(); break;
|
||||
case 0x06F: ASIN(); break;
|
||||
case 0x070: ACOS(); break;
|
||||
case 0x071: ATAN(); break;
|
||||
case 0x072: ATAN2(); break;
|
||||
|
||||
// ── Exponential ─────────────────────────────────
|
||||
case 0x074: EXP(); break;
|
||||
case 0x075: LOG(); break;
|
||||
case 0x076: LOGAB(); break;
|
||||
case 0x077: POW(); break;
|
||||
case 0x078: SQRT(); break;
|
||||
case 0x079: ROOT(); break;
|
||||
|
||||
// ── Integer ─────────────────────────────────────
|
||||
case 0x07C: ADC(); break;
|
||||
case 0x07D: SWC(); break;
|
||||
case 0x07E: MWO(); break;
|
||||
case 0x07F: UMO(); break;
|
||||
|
||||
// ── Matrix ──────────────────────────────────────
|
||||
case 0x080: MADD(); break;
|
||||
case 0x081: MSUB(); break;
|
||||
case 0x082: MMUL(); break;
|
||||
case 0x083: MINV(); break;
|
||||
case 0x084: MTRA(); break;
|
||||
case 0x085: MDET(); break;
|
||||
|
||||
// ── Quaternion ──────────────────────────────────
|
||||
case 0x086: QMKA(); break;
|
||||
case 0x087: QMUL(); break;
|
||||
|
||||
// ── SIMD ────────────────────────────────────────
|
||||
case 0x08A: XADD(); break;
|
||||
case 0x08B: XSUB(); break;
|
||||
case 0x08C: XAMA(); break;
|
||||
case 0x08D: XMUL(); break;
|
||||
case 0x08E: XDIV(); break;
|
||||
|
||||
// ── Easter Eggs ─────────────────────────────────
|
||||
case 0x0F0: UPY(); break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace spider
|
||||
Reference in New Issue
Block a user