diff --git a/autogen/InstructionMasks.hpp b/autogen/InstructionMasks.hpp new file mode 100644 index 0000000..9be8113 --- /dev/null +++ b/autogen/InstructionMasks.hpp @@ -0,0 +1,268 @@ +#pragma once +// AUTO-GENERATED by pygen.ipynb — DO NOT EDIT MANUALLY +#include + +namespace spider { + +// Addressing mode masks — indexed by opcode. +// [opcode][0] = mask for param 1, [opcode][1] = mask for param 2 +constexpr u8 ADDR_MODE_MASKS[][2] = { + { 0x00, 0x00 }, // NOP + { 0x00, 0x00 }, // SPDR + { 0x05, 0x00 }, // MMODE + { 0x1F, 0x00 }, // INT + { 0x1F, 0x00 }, // LRV + { 0x1E, 0x00 }, // FSR + { 0x1E, 0x00 }, // FIR + { 0x1E, 0x00 }, // FZR + { 0x1E, 0x1F }, // LSR + { 0x00, 0x00 }, // FVR + { 0x00, 0x00 }, // MOV + { 0x00, 0x00 }, // MOR + { 0x00, 0x00 }, // AMOV + { 0x04, 0x04 }, // SWP + { 0x04, 0x00 }, // AHM + { 0x00, 0x00 }, // COM + { 0x00, 0x00 }, // NEG + { 0x00, 0x00 }, // EXS + { 0x00, 0x00 }, // INC + { 0x00, 0x00 }, // DEC + { 0x00, 0x00 }, // ADD + { 0x00, 0x00 }, // SUB + { 0x00, 0x00 }, // MUL + { 0x00, 0x00 }, // UMUL + { 0x00, 0x00 }, // DIV + { 0x00, 0x00 }, // UDIV + { 0x00, 0x00 }, // MOD + { 0x00, 0x00 }, // UMOD + { 0x00, 0x00 }, // DMOD + { 0x00, 0x00 }, // UDMD + { 0x00, 0x00 }, // FBT + { 0x00, 0x00 }, // STB + { 0x00, 0x00 }, // CRB + { 0x00, 0x00 }, // TSB + { 0x00, 0x00 }, // BOOL + { 0x00, 0x00 }, // NOT + { 0x00, 0x00 }, // AND + { 0x00, 0x00 }, // OR + { 0x00, 0x00 }, // XOR + { 0x00, 0x00 }, // SHL + { 0x00, 0x00 }, // SHR + { 0x00, 0x00 }, // SSR + { 0x00, 0x00 }, // ROL + { 0x00, 0x00 }, // ROR + { 0x00, 0x00 }, // CNT + { 0x00, 0x00 }, // EQ + { 0x00, 0x00 }, // NE + { 0x00, 0x00 }, // GT + { 0x00, 0x00 }, // GE + { 0x00, 0x00 }, // LT + { 0x00, 0x00 }, // LE + { 0x00, 0x00 }, // JMP + { 0x00, 0x00 }, // JEQ + { 0x00, 0x00 }, // JNE + { 0x00, 0x00 }, // JIF + { 0x00, 0x00 }, // JMR + { 0x00, 0x00 }, // JER + { 0x00, 0x00 }, // JNR + { 0x00, 0x00 }, // JIR + { 0x00, 0x00 }, // SFB + { 0x00, 0x00 }, // LFB + { 0x00, 0x00 }, // JUF + { 0x00, 0x00 }, // JUR + { 0x00, 0x00 }, // PUSH + { 0x00, 0x00 }, // POP + { 0x00, 0x00 }, // ALLOC + { 0x00, 0x00 }, // HFREE + { 0x00, 0x00 }, // CALL + { 0x00, 0x00 }, // RET + { 0x00, 0x00 }, // EDI + { 0x00, 0x00 }, // SHSS + { 0x00, 0x00 }, // FLI + { 0x00, 0x00 }, // FNEG + { 0x00, 0x00 }, // FADD + { 0x00, 0x00 }, // FSUB + { 0x00, 0x00 }, // FMUL + { 0x00, 0x00 }, // FDIV + { 0x00, 0x00 }, // FMOD + { 0x00, 0x00 }, // FDMOD + { 0x00, 0x00 }, // FEPS + { 0x00, 0x00 }, // FEEP + { 0x00, 0x00 }, // FEQ + { 0x00, 0x00 }, // FNE + { 0x00, 0x00 }, // FGT + { 0x00, 0x00 }, // FGE + { 0x00, 0x00 }, // FLT + { 0x00, 0x00 }, // FLE + { 0x00, 0x00 }, // F2D + { 0x00, 0x00 }, // D2F + { 0x00, 0x00 }, // I2F + { 0x00, 0x00 }, // I2D + { 0x00, 0x00 }, // L2F + { 0x00, 0x00 }, // L2D + { 0x00, 0x00 }, // F2I + { 0x00, 0x00 }, // F2L + { 0x00, 0x00 }, // D2I + { 0x00, 0x00 }, // D2L + { 0x00, 0x00 }, // SIN + { 0x00, 0x00 }, // COS + { 0x00, 0x00 }, // TAN + { 0x00, 0x00 }, // ASIN + { 0x00, 0x00 }, // ACOS + { 0x00, 0x00 }, // ATAN + { 0x00, 0x00 }, // ATAN2 + { 0x00, 0x00 }, // EXP + { 0x00, 0x00 }, // LOG + { 0x00, 0x00 }, // LOGAB + { 0x00, 0x00 }, // POW + { 0x00, 0x00 }, // SQRT + { 0x00, 0x00 }, // ROOT + { 0x00, 0x00 }, // ADC + { 0x00, 0x00 }, // SWC + { 0x00, 0x00 }, // MWO + { 0x00, 0x00 }, // UMO + { 0x00, 0x00 }, // MADD + { 0x00, 0x00 }, // MSUB + { 0x00, 0x00 }, // MMUL + { 0x00, 0x00 }, // MINV + { 0x00, 0x00 }, // MTRA + { 0x00, 0x00 }, // MDET + { 0x00, 0x00 }, // XADD + { 0x00, 0x00 }, // XSUB + { 0x00, 0x00 }, // XAMA + { 0x00, 0x00 }, // XMUL + { 0x00, 0x00 }, // XDIV + { 0x00, 0x00 }, // UPY +}; + +// Type size masks — indexed by opcode. +constexpr u8 TYPE_SIZE_MASKS[] = { + 0x00, // NOP + 0x00, // SPDR + 0x01, // MMODE + 0x0F, // INT + 0x0C, // LRV + 0x0F, // FSR + 0x0F, // FIR + 0x0F, // FZR + 0x0F, // LSR + 0x0F, // FVR + 0x00, // MOV + 0x00, // MOR + 0x00, // AMOV + 0x00, // SWP + 0x0F, // AHM + 0x0F, // COM + 0x0F, // NEG + 0x0F, // EXS + 0x0F, // INC + 0x0F, // DEC + 0x0F, // ADD + 0x0F, // SUB + 0x0F, // MUL + 0x0F, // UMUL + 0x0F, // DIV + 0x0F, // UDIV + 0x0F, // MOD + 0x0F, // UMOD + 0x0F, // DMOD + 0x0F, // UDMD + 0x0F, // FBT + 0x0F, // STB + 0x0F, // CRB + 0x0F, // TSB + 0x0F, // BOOL + 0x0F, // NOT + 0x0F, // AND + 0x0F, // OR + 0x0F, // XOR + 0x0F, // SHL + 0x0F, // SHR + 0x0F, // SSR + 0x0F, // ROL + 0x0F, // ROR + 0x0F, // CNT + 0x0F, // EQ + 0x0F, // NE + 0x0F, // GT + 0x0F, // GE + 0x0F, // LT + 0x0F, // LE + 0x0F, // JMP + 0x0F, // JEQ + 0x0F, // JNE + 0x0F, // JIF + 0x0F, // JMR + 0x0F, // JER + 0x0F, // JNR + 0x0F, // JIR + 0x0F, // SFB + 0x0F, // LFB + 0x0F, // JUF + 0x0F, // JUR + 0x0F, // PUSH + 0x0F, // POP + 0x0F, // ALLOC + 0x0F, // HFREE + 0x0F, // CALL + 0x0F, // RET + 0x0F, // EDI + 0x0F, // SHSS + 0x00, // FLI + 0x00, // FNEG + 0x00, // FADD + 0x00, // FSUB + 0x00, // FMUL + 0x00, // FDIV + 0x00, // FMOD + 0x00, // FDMOD + 0x00, // FEPS + 0x00, // FEEP + 0x00, // FEQ + 0x00, // FNE + 0x00, // FGT + 0x00, // FGE + 0x00, // FLT + 0x00, // FLE + 0x00, // F2D + 0x00, // D2F + 0x00, // I2F + 0x00, // I2D + 0x00, // L2F + 0x00, // L2D + 0x00, // F2I + 0x00, // F2L + 0x00, // D2I + 0x00, // D2L + 0x00, // SIN + 0x00, // COS + 0x00, // TAN + 0x00, // ASIN + 0x00, // ACOS + 0x00, // ATAN + 0x00, // ATAN2 + 0x00, // EXP + 0x00, // LOG + 0x00, // LOGAB + 0x00, // POW + 0x00, // SQRT + 0x00, // ROOT + 0x00, // ADC + 0x00, // SWC + 0x00, // MWO + 0x00, // UMO + 0x00, // MADD + 0x00, // MSUB + 0x00, // MMUL + 0x00, // MINV + 0x00, // MTRA + 0x00, // MDET + 0x00, // XADD + 0x00, // XSUB + 0x00, // XAMA + 0x00, // XMUL + 0x00, // XDIV + 0x00, // UPY +}; + +} // namespace spider \ No newline at end of file diff --git a/docs/Spider Instructions.xlsx b/docs/Spider Instructions.xlsx new file mode 100644 index 0000000..1ff5eba Binary files /dev/null and b/docs/Spider Instructions.xlsx differ diff --git a/pygen.ipynb b/pygen.ipynb index b75834b..4d88ae5 100644 --- a/pygen.ipynb +++ b/pygen.ipynb @@ -23,43 +23,52 @@ "name": "stdout", "output_type": "stream", "text": [ - "Repo root : /home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime\n", - "CPU.hpp : /home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime/src/spider/runtime/cpu/CPU.hpp\n", - "XLSX : /home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime/Spider_Instructions.xlsx\n", - "Output dir: /home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime/pygen_out\n" + "Repo root : ./ -> (True)\n", + "CPU.hpp : .//src//spider/runtime/cpu/CPU.hpp -> (True)\n", + "XLSX : .//docs//Spider Instructions.xlsx -> (True)\n", + "Output dir: .//autogen/ -> (True)\n" ] } ], "source": [ "# setup directories\n", - "\n", "import os\n", "\n", - "# Root of the Spider runtime repo — adjust this path to match your machine (folder where spider-runtime lives).\n", - "REPO_ROOT = os.path.abspath('/home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime')\n", + "# [CHANGE]\n", + "# Since we're running on a local environment (i hope)\n", + "# we can just signal a relative directory.\n", + "REPO_ROOT = './'\n", + "DOCS_ROOT = f'{REPO_ROOT}/docs/'\n", + "SRC_ROOT = f'{REPO_ROOT}/src/'\n", "\n", "# Where CPU.hpp lives — this is the file we will inject generated code into.\n", - "CPU_HPP_PATH = os.path.join(REPO_ROOT, 'src', 'spider', 'runtime', 'cpu', 'CPU.hpp')\n", + "CPU_HPP_PATH = f'{SRC_ROOT}/spider/runtime/cpu/CPU.hpp'\n", "\n", "# Where the Excel instruction sheet lives. Allocate the .xlsx file in the project's root folder.\n", - "XLSX_PATH = os.path.join(REPO_ROOT, 'Spider_Instructions.xlsx')\n", + "# NOTE: The file I uploaded has a space instead of underscore!\n", + "XLSX_PATH = f'{DOCS_ROOT}/Spider Instructions.xlsx'\n", "\n", "# Output folder for any standalone generated files.\n", - "OUT_DIR = os.path.join(REPO_ROOT, 'pygen_out')\n", + "OUT_DIR = f'{REPO_ROOT}/autogen/'\n", "\n", "# Create the output directory if it does not exist yet.\n", "# exist_ok=True means no error if it already exists.\n", "os.makedirs(OUT_DIR, exist_ok=True)\n", "\n", - "print(f'Repo root : {REPO_ROOT}')\n", - "print(f'CPU.hpp : {CPU_HPP_PATH}')\n", - "print(f'XLSX : {XLSX_PATH}')\n", - "print(f'Output dir: {OUT_DIR}')\n" + "def dir_exists(path:str):\n", + " return os.path.exists(path) and os.path.isdir(path)\n", + "def file_exists(path:str):\n", + " return os.path.exists(path) and os.path.isfile(path)\n", + "\n", + "print(f'Repo root : {REPO_ROOT } -> ({ dir_exists(REPO_ROOT )})')\n", + "print(f'CPU.hpp : {CPU_HPP_PATH} -> ({file_exists(CPU_HPP_PATH)})')\n", + "print(f'XLSX : {XLSX_PATH } -> ({file_exists(XLSX_PATH )})')\n", + "print(f'Output dir: {OUT_DIR } -> ({ dir_exists(OUT_DIR )})')\n" ] }, { "cell_type": "code", - "execution_count": null, + "execution_count": 5, "id": "b33de8ac", "metadata": {}, "outputs": [ @@ -135,7 +144,7 @@ }, { "cell_type": "code", - "execution_count": null, + "execution_count": 6, "id": "58645013", "metadata": {}, "outputs": [ @@ -154,8 +163,8 @@ "Bit Wise 14\n", "Boolean 12\n", "Branch 12\n", - "Floating Point 10\n", "Casts 10\n", + "Floating Point 10\n", "Memory 9\n", "Trigonometric 7\n", "Exponential 6\n", @@ -271,7 +280,7 @@ }, { "cell_type": "code", - "execution_count": 6, + "execution_count": 7, "id": "452bc76c", "metadata": {}, "outputs": [ @@ -279,7 +288,7 @@ "name": "stdout", "output_type": "stream", "text": [ - "Masks written to: /home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime/pygen_out/InstructionMasks.hpp\n", + "Masks written to: .//autogen/InstructionMasks.hpp\n", "Lines generated : 268\n" ] } @@ -345,7 +354,7 @@ }, { "cell_type": "code", - "execution_count": 7, + "execution_count": 8, "id": "5aaebef0", "metadata": {}, "outputs": [ @@ -367,7 +376,7 @@ " void SPDR();\n", "\n", "\n", - "CPU.hpp updated successfully at: /home/arturobalam/Documents/7thQuarter/Estancia_2/internship-repo/ArturoBalam-Internship2-repo/spider-runtime-folder/spider-runtime/src/spider/runtime/cpu/CPU.hpp\n", + "CPU.hpp updated successfully at: .//src//spider/runtime/cpu/CPU.hpp\n", "Total lines in updated file: 674\n" ] } @@ -440,7 +449,7 @@ ], "metadata": { "kernelspec": { - "display_name": "spider-rntm-env", + "display_name": "Python 3", "language": "python", "name": "python3" }, @@ -454,7 +463,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.12.3" + "version": "3.13.7" } }, "nbformat": 4, diff --git a/src/spider/runtime/cpu/CPU.hpp b/src/spider/runtime/cpu/CPU.hpp index 1e342f8..2bcb302 100644 --- a/src/spider/runtime/cpu/CPU.hpp +++ b/src/spider/runtime/cpu/CPU.hpp @@ -37,6 +37,636 @@ namespace spider { public: // // + // [System] 0x000 — NOP: No Operation + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Nothing + void NOP(); + + // [System] 0x001 — SPDR: Will place the Spider version of the interpreter in RA + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (Spider Version) -> RA + void SPDR(); + + // [System] 0x002 — MMODE: Set Memory Mode + // Params: 1 | AddrMask1: 05 AddrMask2: 00 | TypeMask: 01 + // Operation: Dst -> Memory Mode Bits + void MMODE(); + + // [System] 0x003 — INT: Interrupt + // Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 0F + // Operation: Performs system interrupt no. (Dst) (See table) + void INT(); + + // [System] 0x004 — LRV: Load Interrupt Vector Register + // Params: 1 | AddrMask1: 1F AddrMask2: 00 | TypeMask: 0C + // Operation: Dst -> RV + void LRV(); + + // [System] 0x005 — FSR: Fetch System Register + // Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 0F + // Operation: System Register at Dst -> Dst + void FSR(); + + // [System] 0x006 — FIR: Fetch Instruction Register + // Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 0F + // Operation: Instruction Register -> Dst + void FIR(); + + // [System] 0x007 — FZR: Fetch Stack Base Register + // Params: 1 | AddrMask1: 1E AddrMask2: 00 | TypeMask: 0F + // Operation: Stack Base Register -> Dst + void FZR(); + + // [System] 0x008 — LSR: Load System Register + // Params: 2 | AddrMask1: 1E AddrMask2: 1F | TypeMask: 0F + // Operation: Src -> System Register at Dst + void LSR(); + + // [System] 0x009 — FVR: Fetch Interrupt Vector Register + // Params: 1 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Interrupt Vector Register -> Dst + void FVR(); + + // [Memory] 0x00A — MOV: Moves values + // Params: 2 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Src -> Dst + void MOV(); + + // [Memory] 0x00B — MOR: Moves registers + // Params: 2 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: R Scr -> R Dst + void MOR(); + + // [Memory] 0x00C — AMOV: Array Move, uses X and Y as ptrs, A as amount + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Array from X to Y, by A amount + void AMOV(); + + // [Memory] 0x00D — SWP: Swap registers + // Params: 2 | AddrMask1: 04 AddrMask2: 04 | TypeMask: 00 + // Operation: Src <-> Dst + void SWP(); + + // [Memory] 0x00E — AHM: Ask Host for Memory + // Params: 1 | AddrMask1: 04 AddrMask2: 00 | TypeMask: 0F + // Operation: Asks the host for a specific size of memory. Responds with 0 or 1 + void AHM(); + + // [Integer] 0x010 — COM: One's complement + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: ~ Dst -> Dst + void COM(); + + // [Integer] 0x011 — NEG: Two's complement + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: - Dst -> Dst + void NEG(); + + // [Integer] 0x012 — EXS: Extend Sign + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Last bit is copied and expanded for the next int size + void EXS(); + + // [Integer] 0x013 — INC: Increment + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst + 1 -> Dst + void INC(); + + // [Integer] 0x014 — DEC: Decrement + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst - 1 -> Dst + void DEC(); + + // [Integer] 0x015 — ADD: Addition + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst + Src -> Dst + void ADD(); + + // [Integer] 0x016 — SUB: Subtraction + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst - Src-> Dst + void SUB(); + + // [Integer] 0x017 — MUL: Multiplication + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Signed Dst * Src -> Dst + void MUL(); + + // [Integer] 0x018 — UMUL: Unsigned Multiplication + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Unsigned Dst * Src -> Dst + void UMUL(); + + // [Integer] 0x019 — DIV: Division + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Signed Dst / Src -> Dst + void DIV(); + + // [Integer] 0x01A — UDIV: Unsigned Division + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Unsigned Dst / Src -> Dst + void UDIV(); + + // [Integer] 0x01B — MOD: Modulus + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Signed Dst % Src -> Dst + void MOD(); + + // [Integer] 0x01C — UMOD: Unsigned Modulus + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Unsigned Dst % Src -> Dst + void UMOD(); + + // [Integer] 0x01D — DMOD: Division and Modulus + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Signed Dst / Src -> X, Dst % Src -> Y + void DMOD(); + + // [Integer] 0x01E — UDMD: Unsigned Division and Modulus + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Unsigned Dst / Src -> X, Dst % Src -> Y + void UDMD(); + + // [System] 0x01F — FBT: Test and update Flag Register (Integer) Bits + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Flags of Dst - + void FBT(); + + // [Bit Wise] 0x020 — STB: Set Bit + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Src# bit is set on Dst + void STB(); + + // [Bit Wise] 0x021 — CRB: Clear Bit + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Src# bit is cleared on Dst + void CRB(); + + // [Bit Wise] 0x022 — TSB: Test Bit + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Src# bit is tested against Dst, updates Equal Flag + void TSB(); + + // [Bit Wise] 0x023 — BOOL: Sets the booleaness of a value + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Tests Dst != 0, updates Equal Flag + void BOOL(); + + // [Bit Wise] 0x024 — NOT: Sets the inverse booleaness of a value (! BOOL) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Tests Dst == 0, updates Equal Flag + void NOT(); + + // [Bit Wise] 0x025 — AND: Boolean AND operation + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst AND Src into Dst + void AND(); + + // [Bit Wise] 0x026 — OR: Boolean OR operation + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst OR Src into Dst + void OR(); + + // [Bit Wise] 0x027 — XOR: Boolean XOR operation + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst XOR Src into Dst + void XOR(); + + // [Bit Wise] 0x028 — SHL: Arithmetic Shift Left + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst << Src into Dst + void SHL(); + + // [Bit Wise] 0x029 — SHR: Arithmetic Shift Right + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst >> Src into Dst + void SHR(); + + // [Bit Wise] 0x02A — SSR: Signed Shift Right + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst >>> Src into Dst + void SSR(); + + // [Bit Wise] 0x02B — ROL: Rotate Left + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst ROL Src into Dst + void ROL(); + + // [Bit Wise] 0x02C — ROR: Rotate Right + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst ROR Src into Dst + void ROR(); + + // [Bit Wise] 0x02D — CNT: Counts bits + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: # of 1's into Dst + void CNT(); + + // [Boolean] 0x030 — EQ: Equal + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst == Src into Dst + void EQ(); + + // [Boolean] 0x031 — NE: Not Equal + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst != Src into Dst + void NE(); + + // [Boolean] 0x032 — GT: Greater Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst > Src into Dst + void GT(); + + // [Boolean] 0x033 — GE: Greater or Equal Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst >= Src into Dst + void GE(); + + // [Boolean] 0x034 — LT: Lower Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst < Src into Dst + void LT(); + + // [Boolean] 0x035 — LE: Lower or Equal Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst <= Src into Dst + void LE(); + + // [Branch] 0x038 — JMP: Jump to absolute position + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst -> Instruction Register + void JMP(); + + // [Branch] 0x039 — JEQ: Jumps to position if EQ flag is set + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst -> Instruction Register IF Flags.EQ + void JEQ(); + + // [Branch] 0x03A — JNE: Jumps to position if EQ flag is cleared + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst -> Instruction Register IF NOT Flags.EQ + void JNE(); + + // [Branch] 0x03B — JIF: Jumps if value provided is booleanly true + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst -> Instruction Register IF Src + void JIF(); + + // [Branch] 0x03C — JMR: Jump Relative + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst + Instruction Register -> Instruction Register + void JMR(); + + // [Branch] 0x03D — JER: Jumps to relative position if EQ flag is set + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst + Instruction Register -> Instruction Register IF Flags.EQ + void JER(); + + // [Branch] 0x03E — JNR: Jumps to relative position if EQ flag is cleared + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst + Instruction Register -> Instruction Register IF NOT Flags.EQ + void JNR(); + + // [Branch] 0x03F — JIR: Jumps to relative position if value provided is booleanly true + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst + Instruction Register -> Instruction Register IF Src + void JIR(); + + // [System] 0x040 — SFB: Store (User) Flag Bit + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: + void SFB(); + + // [System] 0x041 — LFB: Load (User) Flag Bit + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: + void LFB(); + + // [Branch] 0x042 — JUF: Jump to absolute position, if user flag is true + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: + void JUF(); + + // [Branch] 0x043 — JUR: Jump to relative position, if user flag is true + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: + void JUR(); + + // [Memory] 0x044 — PUSH: Push to stack + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst -> pushed into stack + void PUSH(); + + // [Memory] 0x045 — POP: Pop from stack + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: popped from stack -> Dst + void POP(); + + // [Memory] 0x046 — ALLOC: Allocate to heap + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Dst -> heap ptr of size Dst + void ALLOC(); + + // [Memory] 0x047 — HFREE: Delete from heap + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Frees heap ptr in Dst + void HFREE(); + + // [Branch] 0x04A — CALL: Call function at instruction index + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Performs a function call, step XX + void CALL(); + + // [Branch] 0x04B — RET: Return from a function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: Undoes a function call, step XX + void RET(); + + // [System] 0x04C — EDI: Enable/Disable External Interrupts + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: bool( Dst ) -> Enable External Interrupts Bit + void EDI(); + + // [System] 0x04D — SHSS: Set Hotswap Signal Bit + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 0F + // Operation: bool( Dst ) -> Hot Swap Signal Bit + void SHSS(); + + // [Floating Point] 0x050 — FLI: Float Load Immediate + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void FLI(); + + // [Floating Point] 0x051 — FNEG: Float negate + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: - Dst -> Dst + void FNEG(); + + // [Floating Point] 0x052 — FADD: Float add + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst + Src -> Dst + void FADD(); + + // [Floating Point] 0x053 — FSUB: Float subtract + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst - Src-> Dst + void FSUB(); + + // [Floating Point] 0x054 — FMUL: Float multiplication + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst * Src -> Dst + void FMUL(); + + // [Floating Point] 0x055 — FDIV: Float division + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst / Src -> Dst + void FDIV(); + + // [Floating Point] 0x056 — FMOD: Float modulus + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst % Src -> Dst + void FMOD(); + + // [Floating Point] 0x057 — FDMOD: Float division and modulus + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst / Src -> X, Dst % Src -> Y + void FDMOD(); + + // [Floating Point] 0x058 — FEPS: Sets the float epsilon value, for comparison + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst -> Epsilon Register + void FEPS(); + + // [Floating Point] 0x059 — FEEP: Float Enable/Disable Epsilon + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: bool( Dst ) -> Epsilon Enable Bit + void FEEP(); + + // [Boolean] 0x05A — FEQ: Float Equal + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst == Src into Dst + void FEQ(); + + // [Boolean] 0x05B — FNE: Float Not Equal + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst != Src into Dst + void FNE(); + + // [Boolean] 0x05C — FGT: Float Greater Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst > Src into Dst + void FGT(); + + // [Boolean] 0x05D — FGE: Float Greater or Equal Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst >= Src into Dst + void FGE(); + + // [Boolean] 0x05E — FLT: Float Lower Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst < Src into Dst + void FLT(); + + // [Boolean] 0x05F — FLE: Float Lower or Equal Than + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst <= Src into Dst + void FLE(); + + // [Casts] 0x060 — F2D: F32 (Float) to F64 (Double) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void F2D(); + + // [Casts] 0x061 — D2F: F64 (Double) to F32 (Float) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void D2F(); + + // [Casts] 0x062 — I2F: I32 (Integer) to F32 (Float) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void I2F(); + + // [Casts] 0x063 — I2D: I32 (Integer) to F64 (Double) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void I2D(); + + // [Casts] 0x064 — L2F: I64 (Long) to F32 (Float) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void L2F(); + + // [Casts] 0x065 — L2D: I64 (Long) to F64 (Double) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void L2D(); + + // [Casts] 0x066 — F2I: F32 (Float) to I32 (Integer) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void F2I(); + + // [Casts] 0x067 — F2L: F32 (Float) to I64 (Long) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void F2L(); + + // [Casts] 0x068 — D2I: F64 (Double) to I32 (Integer) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void D2I(); + + // [Casts] 0x069 — D2L: F64 (Double) to I64 (Long) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: (cast) Dst -> Dst + void D2L(); + + // [Trigonometric] 0x06C — SIN: Sine Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: sin( Dst ) -> Dst + void SIN(); + + // [Trigonometric] 0x06D — COS: Cosine Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: cos( Dst ) -> Dst + void COS(); + + // [Trigonometric] 0x06E — TAN: Tangent Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: tan( Dst ) -> Dst + void TAN(); + + // [Trigonometric] 0x06F — ASIN: Arc Sine Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: asin( Dst ) -> Dst + void ASIN(); + + // [Trigonometric] 0x070 — ACOS: Arc Cosine Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: acos( Dst ) -> Dst + void ACOS(); + + // [Trigonometric] 0x071 — ATAN: Arc Tangent Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: atan( Dst ) -> Dst + void ATAN(); + + // [Trigonometric] 0x072 — ATAN2: Arc Tangent Function with 2 Arguments + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: atan( Dst, Src ) -> Dst + void ATAN2(); + + // [Exponential] 0x074 — EXP: Exponential Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: exp( Dst ) -> Dst + void EXP(); + + // [Exponential] 0x075 — LOG: Natural Logarithm + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: ln( Dst ) -> Dst + void LOG(); + + // [Exponential] 0x076 — LOGAB: Logarithm A of B + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: log( Dst, Src ) -> Dst + void LOGAB(); + + // [Exponential] 0x077 — POW: Power Function + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: pow( Dst, Src ) -> Dst + void POW(); + + // [Exponential] 0x078 — SQRT: Square Root + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: sqrt( Dst ) -> Dst + void SQRT(); + + // [Exponential] 0x079 — ROOT: General Root + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: pow( Dst, 1 / Src ) -> Dst + void ROOT(); + + // [Integer] 0x07C — ADC: Add with Carry + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst + Src + Flags.Carry -> Dst, Flags.Carry + void ADC(); + + // [Integer] 0x07D — SWC: Subtract with Carry (Borrow) + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Dst - Src - Flags.Carry -> Dst, Flags.Carry + void SWC(); + + // [Integer] 0x07E — MWO: Multiply with Overflow + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Signed Dst * Src -> Dst, Flags.Carry + void MWO(); + + // [Integer] 0x07F — UMO: Unsigned Multiply with Overflow + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: Unsigned Dst * Src -> Dst, Flags.Carry + void UMO(); + + // [Matrix] 0x080 — MADD: Matrix Addition + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void MADD(); + + // [Matrix] 0x081 — MSUB: Matrix Subtraction + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void MSUB(); + + // [Matrix] 0x082 — MMUL: Matrix Multiply + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void MMUL(); + + // [Matrix] 0x083 — MINV: Matrix Inverse + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void MINV(); + + // [Matrix] 0x084 — MTRA: Matrix Transpose + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void MTRA(); + + // [Matrix] 0x085 — MDET: Matrix Determinant + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void MDET(); + + // [SIMD] 0x08A — XADD: SIMD Addition + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void XADD(); + + // [SIMD] 0x08B — XSUB: SIMD Subtract + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void XSUB(); + + // [SIMD] 0x08C — XAMA: SIMD Alternate Multiply-Add + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void XAMA(); + + // [SIMD] 0x08D — XMUL: SIMD Multiply + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void XMUL(); + + // [SIMD] 0x08E — XDIV: SIMD Divide + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void XDIV(); + + // [Easter Eggs] 0x0F0 — UPY: Will place "YUPI" in memory + // Params: 0 | AddrMask1: 00 AddrMask2: 00 | TypeMask: 00 + // Operation: + void UPY(); + // // };